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[1]
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Lukas Esterle, Nikil Dutt, Christian Gruhl, Peter R. Lewis, Lucio Marcenaro,
Carlo Regazzoni, and Axel Jantsch.
Self-awareness in Cyber-Physical Systems: Recent Developments
and Open Challenges.
In Design, Automation & Test in Europe Conference &
Exhibition (DATE), 2023.
[ bib |
.pdf ]
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[2]
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Markus D. Kobelrausch and Axel Jantsch.
Skill Acquisition for Resource-Constrained Mobile Robots
through Continuous Exploration.
In Dr. Maki K. Habib, editor, Cognitive Robotics and Adaptive
Behaviors, chapter 3. IntechOpen, Rijeka, 2022.
[ bib |
DOI |
.pdf ]
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[3]
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Daniel Hauer, Maximilian Götzinger, Axel Jantsch, and Florian Kintzler.
Context Aware Monitoring for Smart Grids.
In Proceedings of the International Symposium on Industrial
Electronics (ISIE), Kyoto, Japan, June 2021.
[ bib |
http ]
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[4]
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Bryan Donyanavard, Amir M. Rahmani, Axel Jantsch, Onur Mutlu, and Nikil Dutt.
Intelligent Management of Mobile Systems Through
Computational Self-Awareness.
In Veljko Milutinović and Miloš Kotlar, editors,
Handbook of Research on Methodologies and Applications of Supercomputing,
pages 41--73. IGI Global, Febraury 2021.
[ bib |
DOI |
http ]
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[5]
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Amid Mozelli, Nima Taherinejad, and Axel Jantsch.
A Study on Confidence: an Unsupervised Multi-Agent Machine
Learning Experiment.
IEEE Design & Test of Computers, 2021.
[ bib |
DOI ]
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[6]
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Alexander Wendt, Stefan Kollmann, Aleksey Bratukhin, Alireza Estaji, Thilo
Sauter, and Axel Jantsch.
Cognitive Architectures for Process Monitoring - an
Analysis.
In Proceedings of the 18th IEEE International Conference on
Industrial Informatics, Online, July 2020.
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[7]
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Kerstin Bellman, Nikil Dutt, Lukas Esterle, Andreas Herkersdorf, Axel Jantsch,
C. Landauer, P. R. Lewis, M. Platzner, N. TaheriNejad, and K. Tammemäe.
Self-aware Cyber-Physical Systems.
ACM Transactions on Cyber-Physical Systems, 4(4):1--24, June
2020.
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DOI |
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In this article, we make the case for the new class
of Self-aware Cyber-physical Systems. By bringing
together the two established fields of
cyber-physical systems and self-aware computing, we
aim at creating systems with strongly increased yet
managed autonomy, which is a main requirement for
many emerging and future applications and
technologies. Self-aware cyber-physical systems are
situated in a physical environment and constrained
in their resources, and they understand their own
state and environment and, based on that
understanding, are able to make decisions
autonomously at runtime in a self-explanatory
way. In an attempt to lay out a research agenda, we
bring up and elaborate on five key challenges for
future self-aware cyber-physical systems: (i) How
can we build resource-sensitive yet self-aware
systems? (ii) How to acknowledge situatedness and
subjectivity? (iii) What are effective
infrastructures for implementing self-awareness
processes? (iv) How can we verify self-aware
cyber-physical systems and, in particular, which
guarantees can we give? (v) What novel development
processes will be required to engineer self-aware
cyber-physical systems? We review each of these
challenges in some detail and emphasize that
addressing all of them requires the system to make a
comprehensive assessment of the situation and a
continual introspection of its own state to sensibly
balance diverse requirements, constraints,
short-term and long-term objectives. Throughout, we
draw on three examples of cyber-physical systems
that may benefit from self-awareness: a
multi-processor system-on-chip, a Mars rover, and an
implanted insulin pump. These three very different
systems nevertheless have similar characteristics:
limited resources, complex unforeseeable
environmental dynamics, high expectations on their
reliability, and substantial levels of risk
associated with malfunctioning. Using these
examples, we discuss the potential role of
self-awareness in both highly complex and rather
more simple systems, and as a main conclusion we
highlight the need for research on above listed
topics.
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[8]
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Axel Jantsch, Peter R. Lewis, and Nikil Dutt.
Introduction to the Special Issue on Self-Aware
Cyber-physical Systems.
ACM Transactions on Cyber-Physical Systems, 4(4), June 2020.
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DOI |
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[9]
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David Bechtold, Alexander Wendt, and Axel Jantsch.
Evaluation of Reinforcement Learning Methods for a
Self-learning System.
In Proceedings of the 12th International Conference on Agents
and Artificial Intelligence (ICAART 2020), volume 2, Valletta, Malta,
February 2020.
[ bib |
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[10]
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Maximilian Götzinger, Dávid Juhász, Nima Taherinejad, Edwin Willegger,
Benedikt Tutzer, Pasi Liljeberg, Axel Jantsch, and Amir M. Rahmani.
RoSA: A Framework for Modeling Self-Awareness in
Cyber-Physical Systems.
IEEE Access, 8, 2020.
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DOI |
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[11]
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Henrik Hoffmann, Axel Jantsch, and Nikil Dutt.
Embodied Self-Aware Computing Systems.
Proceedings of the IEEE, pages 1--20, 2020.
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DOI |
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[12]
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Daniel Hauer, Denise Ratasich, Lukas Krammer, and Axel Jantsch.
A Methodology for Resilient Control and Monitoring in Smart
Grids.
In 2020 IEEE International Conference on Industrial Technology
(ICIT), pages 589--594, 2020.
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[13]
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Nima TaheriNejad, Andreas Herkersdorf, and Axel Jantsch.
Autonomous Systems, Trust and Guarantees.
IEEE Design Test, pages 1--1, 2020.
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DOI |
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[14]
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Nima TaheriNejad, Peter Lewis, Axel Jantsch, Amir Rahmani, and Lukas
Esterle.
Resource Constrained Self-Aware Cyber-Physical Systems
(Tutorial).
In 2019 IEEE 4th International Workshops on Foundations and
Applications of Self* Systems (FAS*W), pages 259--260, June 2019.
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DOI ]
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[15]
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Arman Anzanpour, Homayun Rashid, Amir M. Rahmani, Axel Jantsch, Nikil Dutt, ,
and Pasi Liljeberg.
Energy-efficient and Reliable Wearable Internet-of-Things
through Fog-Assisted Dynamic Goal Management.
In Elsevier International Conference on Ambient Systems,
Networks and Technologies (ANT 2019), Belgium, May 2019.
Best Paper Award.
[ bib |
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[16]
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Nima TaheriNejad and Axel Jantsch.
Improved Machine Learning using Confidence.
In IEEE Canadian Conference of Electrical and Computer
Engineering (CCECE), Edmonton, Canada, May 2019.
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.pdf ]
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[17]
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Elham Shamsa, Anil Kanduri, Amir M. Rahmani, Pasi Liljeberg, Axel Jantsch, and
Nikil Dutt.
Goal-Driven Autonomy for Efficient On-chip Resource
Management: Transforming Objectives to Goals.
In Proceedings of the Design and Test Europe Conference (DATE),
Florence, Italy, March 2019.
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[18]
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Axel Jantsch.
Towards a Formal Model of Recursive Self-Reflection.
In International Workshop on Autonomous Systems Design (ASD),
pages 6:1--6:16, March 2019.
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DOI |
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[19]
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Maximilian Götzinger, Nima TaheriNejad, Hedyeh. A. Kholerdi, Axel Jantsch,
Edwin Willegger, T. Glatzl, Amir M. Rahmani, Thilo Sauter, and Pasi
Liljeberg.
Model-free Condition Monitoring with Confidence.
International Journal of Computer Integrated Manufacturing,
32(4-5), 2019.
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DOI |
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[20]
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Maximilian Götzinger, Arman Anzanpour, Iman Azimi, Nima TaheriNejad, Axel
Jantsch, Amir M. Rahmani, and Pasi Liljeberg.
Confidence-Enhanced Early Warning Score Based on Fuzzy
Logic.
Mobile Networks and Applications, 2019.
[ bib |
DOI |
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[21]
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Elham Shamsa, Anil Kanduri, Amir M. Rahmani, Pasi Liljeberg, Axel Jantsch, and
Nikil Dutt.
Goal Formulation: Abstracting Dynamic Objectives for
Efficient On-chip Resource Allocation.
In IEEE Nordic Circuits and Systems Conference (NorCAS),
Tallinn, Estonia, October 2018.
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.pdf ]
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[22]
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Amir M. Rahmani, Axel Jantsch, and Nikil Dutt.
HDGM: Hierarchical Dynamic Goal Management for Many-Core
Resource Allocation.
IEEE Embedded Systems letters, 10(3), September 2018.
[ bib |
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[23]
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Hedyeh A. Kholerdi, Nima TaheriNejad, and Axel Jantsch.
Enhancement of Classification of Small Data Sets Using
Self-awareness - An Iris Flower Case-Study.
In Proceedings of the IEEE International Symposium on Circuits
and Systems (ISCAS), Florence, Italy, May 2018.
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.pdf ]
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[24]
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Lydia Chaido Siafara, Hedyeh Kholerdi, Aleksey Bratukhin, Nima TaheriNejad, and
Axel Jantsch.
SAMBA - An Architecture for Adaptive Cognitive Control of
Distributed Cyber-Physical Production Systems based on its Self-Awareness.
Elektrotechnik & Informationstechnik, 2018.
[ bib |
http ]
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[25]
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Maximilian Götzinger, Edwin Willeger, Nima TaheriNejad, Axel Jantsch, Thilo
Sauter, T. Glatzl, and Pasi Liljeberg.
Applicability of Context-Aware Health Monitoring to Hydraulic
Circuits.
In The 44th Annual Conference of the IEEE Industrial Electronics
Society, 2018.
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[26]
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N. Dutt and A. Jantsch.
Guest Editorial: Special Issue on Self-Aware Systems on
Chip.
IEEE Design Test, 35(5):5--6, Oct 2018.
[ bib |
DOI |
.pdf ]
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[27]
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Axel Jantsch, Nikil Dutt, and Amir M. Rahmani.
Self-Awareness in Systems on Chip -- A Survey.
IEEE Design Test, 34(6):1--19, December 2017.
[ bib |
DOI |
.pdf ]
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[28]
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Nikil Dutt, Amir M. Rahmani, and Axel Jantsch.
Empowering Autonomy through Self-awareness in MPSoCs.
In Proceedings of the IEEE NEWCAS Conference, Strasbourg,
France, June 2017.
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[29]
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M. Wess, P. D. S. Manoj, and A. Jantsch.
Neural network based ECG anomaly detection on FPGA and
trade-off analysis.
In 2017 IEEE International Symposium on Circuits and Systems
(ISCAS), pages 1--4, May 2017.
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DOI |
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[30]
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M. Götzinger, N. TaheriNejad, H. A. Kholerdi, and A. Jantsch.
On the design of context-aware health monitoring without a
priori knowledge; an AC-Motor case-study.
In 2017 IEEE 30th Canadian Conference on Electrical and Computer
Engineering (CCECE), pages 1--5, April 2017.
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DOI |
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[31]
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Arman Anzanpour, Iman Azimi, Maximilian Götzinger, Amir M. Rahmani, Nima
TaheriNejad, Pasi Liljeberg, Axel Jantsch, and Nikil Dutt.
Self-Awareness in Remote Health Monitoring Systems using
Wearable Electronics.
In Proceedings of Design and Test Europe Conference (DATE),
Lausanne, Switzerland, March 2017.
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.pdf ]
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[32]
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Maximilian Götzinger, Martin Pongratz, Amir M. Rahmani, and Axel Jantsch.
Parallelized Flight Path Prediction Using a Graphics
Processing Unit.
In Proceedings of the International Conference on Computer
Vision Theory and Applications (VISAPP), Portugal, February 2017.
[ bib |
.pdf ]
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[33]
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Lydia C. Siafara, Hedyeh A. Kholerdi, Aleksey Bratukhin, Nima TaheriNejad,
Alexander Wendt, Axel Jantsch, Albert Treytl, and Thilo Sauter.
SAMBA: A Self-Aware Health Monitoring Architecture for
Distributed Industrial Systems.
In The 43rd Annual Conference of the IEEE Industrial Electronics
Society, 2017.
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.pdf ]
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[34]
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A. Jantsch and N. Dutt.
Guest Editorial: Special Issue on Self-Aware Systems on
Chip.
IEEE Design Test, 34(6):6--7, Dec 2017.
[ bib |
DOI |
.pdf ]
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[35]
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Maximilian Götzinger, Nima Taherinejad, Amir M. Rahmani, Pasi Liljeberg,
Axel Jantsch, and Hannu Tenhunen.
Enhancing the Early Warning Score System Using Data
Confidence.
In Proceedings of the 6th International Conference on Wireless
Mobile Communication and Healthcare (MobiHealth), Milano, Italy, November
2016.
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[36]
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Nima TaheriNejad, Axel Jantsch, and David Pollreisz.
Comprehensive Observation and its Role in Self-Awareness - An
Emotion Recognition System Example.
In Proceedings of the Federated Conference on Computer Science
and Information Systems, Gdansk, Poland, September 2016.
[ bib |
.pdf ]
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[37]
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Maximilian Götzinger, Amir M. Rahmani, Martin Pongratz, Pasi Liljeberg,
Axel Jantsch, and Hannu Tenhunen.
The Role of Self-Awareness and Hierarchical Agents in
Resource Management for Many-Core Systems.
In International Symposium on Embedded Multicore/Many-core
Systems-on-Chip (MCSoC), Lyon, France, September 2016.
[ bib |
.pdf ]
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[38]
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Nikil Dutt, Axel Jantsch, and Santanu Sarma.
Towards Smart Embedded Systems: A Self-Aware System-on-Chip
Perspective.
ACM Transactions on Embedded Computing Systems, Special Issue on
Innovative Design Methods for Smart Embedded Systems, 15(2):22--27, February
2016.
invited.
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DOI |
.pdf ]
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[39]
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Nikil Dutt, Axel Jantsch, and Santanu Sarma.
Self-Aware Cyber-Physical Systems-on-Chip.
In Proceedings of the International Conference for Computer
Aided Design, Austin, Texas, USA, November 2015.
invited.
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[40]
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J.-S. Preden, K. Tammemäe, A. Jantsch, M. Leier, A. Riid, and E. Calis.
The benefits of self-awareness and attention in fog and mist
computing.
IEEE Computer, Special Issue on Self-Aware/Expressive Computing
Systems, pages 37--45, July 2015.
[ bib |
DOI ]
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[41]
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Axel Jantsch and Kalle Tammemäe.
A Framework of Awareness for Artificial Subjects.
In Proceedings of the 2014 International Conference on
Hardware/Software Codesign and System Synthesis, CODES '14, pages
20:1--20:3, New York, NY, USA, 2014. ACM.
[ bib |
DOI |
http ]
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[42]
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Syed M. A. H. Jafri, Liang Guang, Axel Jantsch, Kolin Paul, Ahmed Hemani, and
Hannu Tenhunen.
Self-Adaptive NoC Power Management with Dual-Level Agents:
Architecture and Implementation.
In Proceedings of the Conference on Self-adaptive Networked
Embedded Systems, Rome, Italy, February 2012.
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.pdf ]
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[43]
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Liang Guang and Axel Jantsch.
Adaptive Power Management for the On-Chip Communication
Network.
In 9th Euromicro Conference on Digital System Design (DSD),
August 2006.
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[1]
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Dewant Katare, Salar Shakibhamedan, Nima Amirafshar, Nima Taherinejad, Axel
Jantsch, Marijn Janssen, and Aaron Yi Ding.
Approximation Strategies for Vision Models on Edge Devices:
An Accuracy-Efficiency Trade-off.
In TechRxiv. December 2024.
[ bib |
DOI |
.pdf ]
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[2]
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Axel Jantsch, Song Han, Lin Meng, Oliver Bringmann, Haotian Tang, Shang Yang,
Hengyi Li, Matthias Wess, and Martin Lechner.
Special Session: Estimation and Optimization of DNNs for
Embedded Platforms.
In Proceedings of the International Symposium on Hardware
Software Codesign, pages 21--30, Raleigh, NC, October 2024.
[ bib |
DOI ]
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[3]
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Salar Shakibhamedan, Amin Aminifar, Nima Taherinejad, and Axel Jantsch.
EASE: Energy Optimization through Adaptation - A Review of
Runtime Energy-Aware Approximate Deep Learning Algorithms.
In TechRxiv. February 2024.
[ bib |
DOI |
.pdf ]
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[4]
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Matthias Wess, Daniel Schnöll, Dominik Dallinger, Matthias Bittner, and
Axel Jantsch.
Conformal Prediction based Confidence for Latency Estimation
of DNN Accelerators: A Black-box Approach.
IEEE Access, 2024.
[ bib |
DOI |
.pdf ]
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[5]
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Martin Lechner and Axel Jantsch.
Hardware-Aware Latency Pruning for Efficient Inference on
Embedded GPUs.
Under submission, 2024.
[ bib ]
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[6]
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David Breuss, Karel Rusý, Maximilian Götzinger, and Axel Jantsch.
Generation of Synthetic Image Anomalies for Analysis and
Evaluation.
In Proceedings of the International Conference on Intelligent
Systems and Pattern Recognition, 2024.
[ bib |
.pdf ]
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[7]
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Thomas Leopold and Axel Jantsch.
Colorado Potato Beetle Dataset and Detection for Monitoring
and Management in Potato Fields.
In Proceedings of the Austrian Symposion on AI, Robotics and
Vision, Austria, 2024.
[ bib |
.pdf ]
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[8]
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Matthias Bittner1, Daniel Hauer, Matthias Wess, Dominik Dallinger, Daniel
Schnöll1, Konrad Diwold, and Axel Jantsch.
Interpretable Load Forecasting with Structured State Space
Neural Networks.
In Proceedings of the European Conference on Machine Learning
and Principles and Practice of Knowledge Discovery in Databases, 2024.
[ bib ]
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[9]
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Matthias Bittner, Daniel Hauer, Matthias Wess, Daniel Schnöll, Konrad Diwold,
and Axel Jantsch.
Forecasting Load Profiles and Critical Overloads with
Uncertainty Quantification for Low Voltage Smart Grids.
In Proceedings of the The 8th International Conference on System
Reliability and Safety, Novemebr 2024.
[ bib ]
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[10]
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Matthias Bittner, Daniel Hauer, Christian Stippel, Katharina Scheucher, Robin
Sudhoff, and Axel Jantsch.
Forecasting Critical Overloads based on Heterogeneous Smart
Grid Simulation.
In Proceedings of the International Conference on Machine
Learning and Applications (ICMLA, Jacksonville, Florida, USA, December 2023.
IEEE and AMLA.
[ bib |
.pdf ]
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[11]
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Matthias Wess, Dominik Dallinger, Daniel Schnöll, Matthias Bittner,
Maximilian Götzinger, and Axel Jantsch.
Energy Profiling of DNN Accelerators.
In Proceedings of the 26th Euromicro Conference on Digital
System Design (DSD), Durres, Albania, September 2023.
[ bib |
.pdf ]
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[12]
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David Breuss, Maximilian Götzinger, Jenny Vuong, Clemens Reisner, and Axel
Jantsch.
VADAR: A Vision-based Anomaly Detection Algorithm for
Railroads.
In Proceedings of the 26th Euromicro Conference on Digital
System Design (DSD), Durres, Albania, September 2023.
[ bib |
.pdf ]
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[13]
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Daniel Schnöll, Matthias Wess, Matthias Bittner, Maximilian Götzinger,
and Axel Jantsch.
Fast, Quantization Aware DNN Training for Efficient HW
Implementation.
In Proceedings of the 26th Euromicro Conference on Digital
System Design (DSD), Durres, Albania, September 2023.
[ bib |
.pdf ]
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[14]
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Isaac Sánchez Leal, Eiraj Saqib, Irida Shallari, Axel Jantsch, Silvia Krug,
and Mattias O'Nils.
Waist Tightening of CNNs: A Case study on Tiny YOLOv3 for
Distributed IoT Implementations.
In Proceedings of the Real-time And intelliGent Edge computing
workshop (RAGE), San Antonio, Texas, May 2023.
[ bib |
http ]
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[15]
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Thomas Kotrba, Martin Lechner, Omair Sarwar, and Axel Jantsch.
Multispectral Feature Fusion for Deep Object Detection on
Embedded Nvidia Platforms.
In Design, Automation & Test in Europe Conference &
Exhibition (DATE), Antwerp, Belgium, April 2023.
[ bib |
.pdf ]
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[16]
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Alexander Wendt, Horst Possegger, Matthias Bittner, Daniel Schnöll,
Matthias Wess, Dušan Malić, Horst Bischof, and Axel Jantsch.
A Pedestrian Detection Case Study for a Traffic Light
Controller.
In Sudeep Pasricha and Muhammad Shafique, editors, Embedded
Machine Learning for Cyber-Physical, IoT, and Edge Computing - Software
Optimizations and Hardware/Software Codesign, pages 75--96. Springer, 2023.
[ bib |
DOI |
http ]
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[17]
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Eiraj Saqib, Isaac Sánchez Leal, Irida Shallari, Axel Jantsch, Silvia Krug,
and Mattias O'Nils.
Optimizing the IoT Performance: A Case Study on Pruning a
Distributed CNN.
In Proceedings of the IEEE Sensors Applications Symposium
(SAS), 2023.
[ bib |
.pdf ]
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[18]
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Matthias Bittner, Sanaa Hobeichi, Muhammad Zawish, Samo Diatta, Remigious
Ozioko, Sharon Xu, and Axel Jantsch.
An LSTM-based Downscaling Framework for Australian
Precipitation Projections.
In NeurIPS 2023 Workshop: Tackling Climate Change with Machine
Learning at the Conference on Neural Information Processing Systems,
December, 2023.
[ bib |
.pdf ]
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[19]
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Martin Lechner, Axel Jantsch, and Lukas Steindl.
Study of DNN-based Ragweed Detection from Drones.
In Proceedings of International Conference on Embedded Computer
Systems: Architectures, Modeling and Simulation (SAMOS), Samos, Greece, July
2022.
[ bib |
.pdf ]
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[20]
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Adam Lundström, Mattias O'Nils, Faisal Qureshi, and Axel Jantsch.
Improving deep learning based anomaly detection on
multivariate time series through separated anomaly scoring.
IEEE Access, pages 1--1, 2022.
[ bib |
DOI ]
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[21]
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Bernhard Haas, Alexander Wendt, Axel Jantsch, and Matthias Wess.
Neural Network Compression Through Shunt Connections and
Knowledge Distillation for Semantic Segmentation Problems.
In 17th International Conference on Artificial Intelligence
Applications and Innovations (AIAI), June 2021.
[ bib |
DOI |
http ]
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[22]
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Alessio Colucci, Dávid Juhász, Martin Mosbeck, Alberto Marchisio, Semeen
Rehman, Manfred Kreutzer, Günter Nadbath, Axel Jantsch, and Muhammad
Shafique.
MLComp: A Methodology for Machine Learning-based
Performance Estimation and Adaptive Selection of Pareto-Optimal Compiler
Optimization Sequences.
In Proceedings of the Design, Automation and Test in Europe
Conference and Exhibition, March 2021.
[ bib |
.pdf ]
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[23]
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Matthias Wess, Marco Ivanov, Christian Unger, Anvesh Nookala, Alexander Wendt,
and Axel Jantsch.
ANNETTE: Accurate Neural Network Execution Time Estimation
With Stacked Models.
IEEE Access, 9:3545--3556, 2021.
[ bib |
DOI |
.pdf ]
With new accelerator hardware for Deep Neural
Networks (DNNs), the computing power for Artificial
Intelligence (AI) applications has increased
rapidly. However, as DNN algorithms become more
complex and optimized for specific applications,
latency requirements remain challenging, and it is
critical to find the optimal points in the design
space. To decouple the architectural search from the
target hardware, we propose a time estimation
framework that allows for modeling the inference
latency of DNNs on hardware accelerators based on
mapping and layer-wise estimation models. The
proposed methodology extracts a set of models from
micro-kernel and multi-layer benchmarks and
generates a stacked model for mapping and network
execution time estimation. We compare estimation
accuracy and fidelity of the generated mixed models,
statistical models with the roofline model, and a
refined roofline model for evaluation. We test the
mixed models on the ZCU102 SoC board with Xilinx
Deep Neural Network Development Kit (DNNDK) and
Intel Neural Compute Stick 2 (NCS2) on a set of 12
state-of-the-art neural networks. It shows an
average estimation error of 3.47% for the DNNDK and
7.44% for the NCS2, outperforming the statistical
and analytical layer models for almost all selected
networks. For a randomly selected subset of 34
networks of the NASBench dataset, the mixed model
reaches fidelity of 0.988 in Spearman’s ρ rank
correlation coefficient metric.
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[24]
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Martin Lechner and Axel Jantsch.
Blackthorn: Latency Estimation Framework for CNNs on
Embedded Nvidia Platforms.
IEEE Access, 2021.
[ bib |
DOI |
.pdf ]
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[25]
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Irida Shallari, Isaac Sánchez Leal, Silvia Krug, Axel Jantsch, and Mattias
O'Nils.
Design space exploration on IoT node: Trade-offs in
processing and communication.
IEEE Access, 2021.
[ bib |
DOI |
.pdf ]
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[26]
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Isaac Sánchez Leal, Irida Shallari, Silvia Krug, Axel Jantsch, and Mattias
O'Nils.
Impact of Input Data on Intelligence Partitioning Decisions
for IoT Smart Camera Nodes.
Electronics, 10(16), 2021.
[ bib |
DOI |
.pdf ]
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[27]
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Amid Mozelli, Nima Taherinejad, and Axel Jantsch.
A Study on Confidence: an Unsupervised Multi-Agent Machine
Learning Experiment.
IEEE Design & Test of Computers, 2021.
[ bib |
DOI ]
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[28]
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Kerstin Bellman, Nikil Dutt, Lukas Esterle, Andreas Herkersdorf, Axel Jantsch,
C. Landauer, P. R. Lewis, M. Platzner, N. TaheriNejad, and K. Tammemäe.
Self-aware Cyber-Physical Systems.
ACM Transactions on Cyber-Physical Systems, 4(4):1--24, June
2020.
[ bib |
DOI |
.pdf ]
In this article, we make the case for the new class
of Self-aware Cyber-physical Systems. By bringing
together the two established fields of
cyber-physical systems and self-aware computing, we
aim at creating systems with strongly increased yet
managed autonomy, which is a main requirement for
many emerging and future applications and
technologies. Self-aware cyber-physical systems are
situated in a physical environment and constrained
in their resources, and they understand their own
state and environment and, based on that
understanding, are able to make decisions
autonomously at runtime in a self-explanatory
way. In an attempt to lay out a research agenda, we
bring up and elaborate on five key challenges for
future self-aware cyber-physical systems: (i) How
can we build resource-sensitive yet self-aware
systems? (ii) How to acknowledge situatedness and
subjectivity? (iii) What are effective
infrastructures for implementing self-awareness
processes? (iv) How can we verify self-aware
cyber-physical systems and, in particular, which
guarantees can we give? (v) What novel development
processes will be required to engineer self-aware
cyber-physical systems? We review each of these
challenges in some detail and emphasize that
addressing all of them requires the system to make a
comprehensive assessment of the situation and a
continual introspection of its own state to sensibly
balance diverse requirements, constraints,
short-term and long-term objectives. Throughout, we
draw on three examples of cyber-physical systems
that may benefit from self-awareness: a
multi-processor system-on-chip, a Mars rover, and an
implanted insulin pump. These three very different
systems nevertheless have similar characteristics:
limited resources, complex unforeseeable
environmental dynamics, high expectations on their
reliability, and substantial levels of risk
associated with malfunctioning. Using these
examples, we discuss the potential role of
self-awareness in both highly complex and rather
more simple systems, and as a main conclusion we
highlight the need for research on above listed
topics.
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[29]
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David Bechtold, Alexander Wendt, and Axel Jantsch.
Evaluation of Reinforcement Learning Methods for a
Self-learning System.
In Proceedings of the 12th International Conference on Agents
and Artificial Intelligence (ICAART 2020), volume 2, Valletta, Malta,
February 2020.
[ bib |
http ]
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[30]
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Henrik Hoffmann, Axel Jantsch, and Nikil Dutt.
Embodied Self-Aware Computing Systems.
Proceedings of the IEEE, pages 1--20, 2020.
[ bib |
DOI |
.pdf ]
|
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[31]
|
Nima TaheriNejad, Andreas Herkersdorf, and Axel Jantsch.
Autonomous Systems, Trust and Guarantees.
IEEE Design Test, pages 1--1, 2020.
[ bib |
DOI |
.pdf ]
|
|
[32]
|
Muhammad Abdullah Hanif, Muhammad Zuhaib Akbar, Rehan Ahmed, Semeen Rehman,
Axel Jantsch, and Muhammad Shafique.
MemGANs: Memory Management for Energy-Efficient
Acceleration of Complex Computations in Hardware Architectures for Generative
Adversarial Networks.
In Proceesings of the International Symposium on Low Power
Electronics and Design (ISLPED), Lausanne, Switzerland, July 2019.
[ bib |
.pdf ]
|
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[33]
|
Nima TaheriNejad and Axel Jantsch.
Improved Machine Learning using Confidence.
In IEEE Canadian Conference of Electrical and Computer
Engineering (CCECE), Edmonton, Canada, May 2019.
[ bib |
.pdf ]
|
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[34]
|
Martin Lechner, Axel Jantsch, and Sai M. P. Dinakarrao.
ResCoNN: Resource-Efficient FPGA-Accelerated CNN for
Traffic Sign Classification.
In 2019 Tenth International Green and Sustainable Computing
Conference (IGSC), pages 1--6, Oct 2019.
[ bib |
DOI ]
|
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[35]
|
Matthias Wess, Sai Manoj Pudukotai Dinakarrao, and Axel Jantsch.
Weighted Quantization-Regularization in DNNs for Weight
Memory Minimization towards HW Implementation.
IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, 37(10), October 2018.
[ bib |
DOI |
.pdf ]
|
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[36]
|
Santiago Pagani, Sai Manoj P D, Axel Jantsch, and Jörg Henkel.
Machine Learning for Power, Energy, and Thermal Management on
Multi-core Processors: A Survey.
IEEE Transaction on Computer Aided Design (TCAD), 2018.
[ bib |
DOI |
.pdf ]
|
|
[1]
|
Marcelo Ruaro, Axel Jantsch, and Fernando Gehm Moraes.
Self-Adaptive QoS Management of Computation and
Communication Resources in Many-Core SoCs.
ACM Transactions on Embedding Computing Systems,
18(4):37:1--37:21, June 2019.
[ bib |
DOI |
http ]
|
|
[2]
|
Junshi Wang, M. Ebrahimi, L. Huang, X. Xie, Q. Li, G. Li, and A. Jantsch.
Efficient Design-for-Test Approach for Networks-on-Chip.
IEEE Transactions on Computers, 68(2):198--213, February 2019.
[ bib |
DOI |
.pdf ]
|
|
[3]
|
Marcelo Ruaro, Nedison Velloso, Axel Jantsch, and Fernando G. Moraes.
Distributed SDN Architecture for NoC-Based Many-Core
SoCs.
In Proceedings of the 13th IEEE/ACM International Symposium on
Networks-on-Chip, NOCS ’19, New York, NY, USA, 2019. Association for
Computing Machinery.
[ bib |
DOI |
http ]
|
|
[4]
|
Fahimeh Jafari, Axel Jantsch, and Zhonghai Lu.
Weighted Round Robin Configuration for Worst-Case Delay
Optimization in Network-on-Chip.
IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, 24(12), May 2016.
[ bib |
DOI ]
|
|
[5]
|
Awet Yemane Weldezion, Matt Grange, Axel Jantsch, Hannu Tenhunen, and Dinesh
Pamunuwa.
Zero-Load Predictive Model for Performance Analysis in
Deflection Routing NoCs.
Journal of Microprocessors and Microsystems, 39(8), November
2015.
[ bib |
DOI ]
|
|
[6]
|
Shaoteng Liu, Zhonghai Lu, and Axel Jantsch.
Highway in TDM NoCs.
In Proceedings of the International Symposium on Networks on
Chip, Vancouver, Canada, September 2015.
Best Paper Award.
[ bib |
.pdf ]
|
|
[7]
|
Fahimeh Jafari, Zhonghai Lu, and Axel Jantsch.
Least Upper Delay Bound for VBR Flows in Networks-on-Chip
with Virtual Channels.
ACM Trans. Design Autom. Electr. Syst., 20(3):35:1--35:33,
June 2015.
[ bib |
DOI |
http ]
|
|
[8]
|
Runan Ma, Zhida Hui, and Axel Jantsch.
A Packet-switched Interconnect for Many-core Systems with
BE and RT Service.
In Proceedings of the Design Automation and Test Europe
Conference (DATE), Grenoble, France, March 2015.
[ bib |
DOI ]
|
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[9]
|
Shaoteng Liu, Axel Jantsch, and Zhonghai Lu.
MultiCS: Circuit Switched NoC with Multiple Sub-Networks
and Sub-Channels.
Journal of Systems Architecture, 2015.
[ bib |
DOI |
.pdf ]
|
|
[10]
|
Shaoteng Liu, Axel Jantsch, and Zhonghai Lu.
Parallel Probe Based Dynamic Connection Setup in TDM
NoCs.
In Proceedings of the Design Automation and Test Europe
Conference (DATE), March 2014.
[ bib |
.pdf ]
|
|
[11]
|
Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Yang Guo, and Hengzhu
Liu.
Cooperative communication for efficient and scalable
all-to-all barrier synchronization on mesh-based many-core NoCs.
IEICE Electronics Express, 11(18):20140542--20140542, 2014.
[ bib |
DOI ]
|
|
[12]
|
Ahsen Ejaz and Axel Jantsch.
Costs and Benefits of Flexibility in Spatial Division Circuit
Switched Networks-on-Chip.
In Proceedings of the Sixth International Workshop on Network on
Chip Architecture, Davis, CA, December 2013.
[ bib |
http ]
|
|
[13]
|
Jiajie Zhang, Zheng Yu, Zhiyi Yu, Kexin Zhang, Zhonghai Lu, and Axel Jantsch.
Efficient Distributed Memory Management in a Multi-Core
H.264 Decoder on FPGA.
In Proceedings of the International Symposium on System on
Chip, Tampere, Finland, October 2013.
[ bib |
.pdf ]
|
|
[14]
|
Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa, Axel Jantsch, and Hannu
Tenhunen.
A Scalable Multi-Dimensional NoC Simulation Model for
Diverse Spatio-temporal Traffic Pattern.
In Proceedings of the 3D Systems Integration Conference
(3DIC), San Francisco, California, USA, October 2013.
[ bib |
.pdf ]
|
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[15]
|
Shaoteng Liu, Axel Jantsch, and Zhonghai Lu.
Analysis and evaluation of circuit switched NoC and packet
switch NoC.
In Proceedings of Euromicro Digital System Design Conference,
Santander, Spain, September 2013.
[ bib |
.pdf ]
|
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[16]
|
Martin Radetzki, Chaochao Feng, Xueqian Zhao, and Axel Jantsch.
Methods for Fault Tolerance in Networks-on-Chip.
ACM Computing Surveys, 46(1):8:1--8:38, July 2013.
[ bib |
DOI |
http ]
|
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[17]
|
Abbas Eslami Kiasari, Axel Jantsch, and Zhonghai Lu.
Mathematical Formalisms for Performance Evaluation of
Networks-on-Chip.
ACM Computing Surveys, 45(3), June 2013.
[ bib |
DOI |
.pdf ]
|
|
[18]
|
Chaochao Feng, Zhonghai Lu, Axel Jantsch, Minxuan Zhang, and Zuocheng Xing.
Addressing Transient and Permanent Faults in NoC With
Efficient Fault-Tolerant Deflection Router.
IEEE Transactions on Very Large Scale Integration Systems
(TVLSI), 21(6):1053--1066, June 2013.
[ bib |
.pdf ]
|
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[19]
|
Abbas Eslami Kiasari, Zhonghai Lu, and Axel Jantsch.
An Analytical Latency Model for Networks-on-Chip.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions
on, 21(1):113 --123, January 2013.
[ bib |
DOI |
.pdf ]
|
|
[20]
|
Abdul Naeem, Axel Jantsch, and Zhonghai Lu.
Scalability Analysis of Release and Sequential Consistency
Models in NoC based Multicore Systems.
In Proceedings of the International Symposium on Systems on
Chip, Tampere, Finland, October 2012.
[ bib |
.pdf ]
|
|
[21]
|
Abdul Naeem, Axel Jantsch, and Zhonghai Lu.
Architecture Support and Comparison of Three Memory
Consistency Models in NoC based Systems.
In Proceedings of the Euromicro Conference on Digital Systems
Design (DSD), Izmir, Turkey, September 2012.
[ bib |
.pdf ]
|
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[22]
|
Chaochao Feng, Zhonghai Lu, Axel Jantsch, and Minxuan Zhang.
A 1-cycle 1.25GHz Bufferless Router for 3D
Network-on-Chip.
IEICE Transactions on Information and Systems, May 2012.
[ bib |
.pdf ]
|
|
[23]
|
Shaoteng Liu, Axel Jantsch, and Zhonghai Lu.
Parallel Probing: Dynamic and Constant Time Setup Procedure
in Circuit Switching NoCs.
In Proceedings of the Design and Test in Europe Conference
(DATE), Dresden, Germany, March 2012.
[ bib |
.pdf ]
|
|
[24]
|
Fahimeh Jafari, Axel Jantsch, and Zhonghai Lu.
Worst-Case Delay Analysis of Variable Bit-Rate Flows in
Network-on-Chip with Aggregate Scheduling.
In Proceedings of the Design and Test in Europe Conference
(DATE), Dresden, Germany, March 2012.
[ bib |
.pdf ]
|
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[25]
|
Syed M. A. H. Jafri, Liang Guang, Axel Jantsch, Kolin Paul, Ahmed Hemani, and
Hannu Tenhunen.
Self-Adaptive NoC Power Management with Dual-Level Agents:
Architecture and Implementation.
In Proceedings of the Conference on Self-adaptive Networked
Embedded Systems, Rome, Italy, February 2012.
[ bib |
.pdf ]
|
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[26]
|
Shaoteng Liu, Axel Jantsch, and Zhonghai Lu.
Comparison of Circuit Switched NoC with Packet Switched
NoC.
In Fifth Swedish Workshop on Multicore Computing, Stockholm,
Sweden, 11 2012.
[ bib ]
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[27]
|
Chaochao Feng, Zhonghai Lu, Axel Jantsch, Minxuan Zhang, and Xianju Yang.
Support Efficient and Fault-tolerant Multicast in Bufferless
Network-on-Chip.
IEICE Transactions on Information and Systems, 2012.
[ bib |
.pdf ]
|
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[28]
|
Fahimeh Jafari, Axel Jantsch, and Zhonghai Lu.
Output Process of Variable Bit-Rate Flows in On-Chip Networks
Based on Aggregate Scheduling.
In Proceedings of the International Conference on Computer
Design, Amherst, Massachusetts, USA, October 2011.
[ bib |
.pdf ]
|
|
[29]
|
Wenmin Hu, Zhonghai Lu, Axel Jantsch, Hengzhu Liu, Botao Zhang, and Dongpei
Liu.
Network-on-Chip Multicasting with Low Latency Path Setup.
In Proceedings of the VLSI-SoC Conference, October 2011.
[ bib |
.pdf ]
|
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[30]
|
Chaochao Feng, Jinwen Li, Zhonghai Lu, Axel Jantsch, and Minxuan Zhang.
Evaluation of Deflection Routing on Various NoC
Topologies.
In Proceedings of the IEEE International Conference on ASIC
(ASICON), Xiamen, China, October 2011.
[ bib |
.pdf ]
|
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[31]
|
Abdul Naeem, Axel Jantsch, Xiaowen Chen, and Zhonghai Lu.
Realization and Scalability of Release and Protected Release
Considtency Models in NoC based Systems.
In Proceedings of the Euromicro Conference on Digital Systems
Design (DSD), Oulu, Finland, September 2011.
[ bib |
.pdf ]
|
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[32]
|
Meganathan Deivasigamani, Shaghayeghsadat Tabatabaei, Naveed Mustafa, Hamza
Ijaz, Haris Bin Aslam, Shaoteng Liu, and Axel Jantsch.
Concept and Design of Exhaustive-Parallel search algorithm
for Network-on-Chip.
In Proceedings of the International SoC Conference, pages
150--155, September 2011.
[ bib |
.pdf ]
|
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[33]
|
Chaochao Feng, Zhonghai Lu, Axel Jantsch, Minxuan Zhang, Jinwen Li, and Jiang
Jiang.
A Low-overhead Fault-aware Deflection Routing Algorithm for
3D Network-on-Chip.
In Proceedings of the IEEE Annual Symposium on VLSI (ISVLSI),
Chennai, India, July 2011.
[ bib |
.pdf ]
|
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[34]
|
Matt Grange, Roshan Weerasekera, Dinesh Pamunuwa, Axel Jantsch, and Awet Yemane
Weldezione.
Optimal Network Architectures for Minimizing Average Distance
in k-ary n-dimensional Mesh Networks.
In Proceedings of the Networks on Chip Symposium (NoCS),
Pittsburgh, Pennsylvania, USA, May 2011.
[ bib |
.pdf ]
|
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[35]
|
Axel Jantsch and Dimitrios Soudris, editors.
Scalable Multi-core Architectures: Design, Methodologies, and
Tools.
Springer, 2011.
[ bib ]
|
|
[36]
|
Abdul Naeem, Xiaowen Chen, Zhonghai Lu, and Axel Jantsch.
Realization and Performance Comparison of Sequential and Weak
Memory Consistency Models in Network-on-Chip based Multi-core Systems.
In Proceedings of the 16th Asian Pacific Design Automation
Conference (ASP-DAC), Tokyo, Japan, January 2011.
[ bib |
.pdf ]
|
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[37]
|
Axel Jantsch, Xiaowen Chen, Abdul Naeem, Yuang Zhang, Sandro Penolazzi, and
Zhonghai Lu.
Memory Architecture and Management in an NoC Platform.
In Axel Jantsch and Dimitrios Soudris, editors, Scalable
Multi-core Architectures: Design Methodologies and Tools. Springer, 2011.
[ bib |
.pdf ]
|
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[38]
|
Wenmin Hu, Zhonghai Lu, Axel Jantsch, and Hengzhu Liu.
Power-efficient Tree-based Multicast Support for
Networks-on-Chip.
In Proceedings of the Asian Pacific Design Automation Conference
(ASPDAC), Tokyo, Japan, January 2011.
[ bib |
.pdf ]
|
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[39]
|
Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, and Hai Liu.
Cooperative communication based barrier synchronization in
on-chip mesh architectures.
IEICE Electronics Express, 8(22):1856--1862, 2011.
[ bib |
www: ]
|
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[40]
|
Bernard Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos,
Sotirios Xydis, Alexandros Bartzas, Dimitris Bekiaris, Dimitrios Soudris,
Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, Ahmed Hemani, Axel Jantsch,
Geert Vanmeerbeeck, Jari Kreku, Kari Tiensyrja, Fragkiskos Ieromnimon,
Dimitrios Kritharidis, Andreas Wiefrink, Bart Vanthournout, and Philippe
Martin.
The MOSART Mapping Optimization for multi-core
Architectures.
In Designing Very Large Scale Integration Systems: Emerging
Trends and Challenges. Springer, 2011.
[ bib |
.pdf ]
|
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[41]
|
Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Zhonghai Lu,
Dimitrios Soudris, and Axel Jantsch.
Custom Microcoded Dynamic Memory Management for Distributed
On-Chip Memory Organizations.
IEEE Embedded Systems Letters, 2011.
[ bib |
.pdf ]
|
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[42]
|
Fahimeh Jafari, Zhonghai Lu, Axel Jantsch, and Mohammad Hossein Yaghmaee.
Buffer Optimization in Network-on-Chip Through Flow
Regulation.
IEEE Transactions on Computer Aided Design (TCAD),
29(12):1973--1986, December 2010.
[ bib |
http ]
|
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[43]
|
Xiaowen Chen, Zhonghai Lu, Shuming Chen, and Axel Jantsch.
Run-time Partitioning of Hybrid Distributed Shared Memory on
Multi-core Network-on-Chips.
In The 3rd IEEE International Symposium on Parallel
Architectures, Algorithms and Programming (PAAP 2010), Dalian, China,
December 2010.
[ bib |
.pdf ]
|
|
[44]
|
Abbas Eslami Kiasari, Axel Jantsch, and Zhonghai Lu.
A Framework for Designing Congestion-Aware Deterministic
Routing.
In Proceedings of the International Workshop on Network on Chip
Architectures (NoCArc), Atlanta, Gorgia, November 2010.
[ bib |
.pdf ]
|
|
[45]
|
Chaochao Feng, Zhonghai Lu, Axel Jantsch, Jinwen Li, and Minxuan Zhang.
A Reconfigurable Fault-tolerant Deflection Routing Algorithm
Based on Reinforcement Learning for Networks-on-Chip.
In Proceedings of the International Workshop on Network on Chip
Architectures (NoCArc), Atlanta, Gorgia, November 2010.
[ bib |
.pdf ]
|
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[46]
|
Xiaowen Chen, Shuming Chen, Zhonghai Lu, and Axel Jantsch.
Multi-FPGA Implementation of a Network-on-Chip Based
Many-core Architecture with Fast Barrier Synchronization Mechanism.
In Proceedings of the IEEE Norchip Conference, Tampere,
Finland, November 2010.
[ bib |
.pdf ]
|
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[47]
|
Xiaowen Chen, Shuming Chen, Zhonghai Lu, and Axel Jantsch.
Area and Performance Optimization of Barrier Synchronization
on Multi-core Network-on-Chips.
In 3rd IEEE International Conference on Computer and Electrical
Engineering (ICCEE), Chengdu, China, November 2010.
[ bib |
.pdf ]
|
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[48]
|
Chaochao Feng, Zhonghai Lu, Axel Jantsch, Jinwen Li, and Minxuan Zhang.
FoN: Fault-on-Neighbor aware Routing Algorithm for
Networks-on-Chip.
In International SOC Conference, Las Vegas, Nevada, September
2010.
[ bib |
.pdf ]
|
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[49]
|
Zhipeng Chen and Axel Jantsch.
A Worst Case performance model for TDM Virtual Circuit in
NOCs.
In Proceedings of the International Workshop on Network on
Chip, Zheng Zhou, China, September 2010.
[ bib |
.pdf ]
|
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[50]
|
Xiaowen Chen, Zhonghai Lu, Axel Jantsch, and Shuming Chen.
Handling Shared Variable Synchronization in Multi-core
Network-on-Chip with Distributed Memory.
In International SOC Conference, Las Vegas, Nevada, September
2010.
[ bib |
.pdf ]
|
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[51]
|
Xiaowen Chen, Zhonghai Lu, Axel Jantsch, and Shuming Chen.
Supporting Efficient Synchronization in Multi-core NoCs
Using Dynamic Buffer Allocation Technique.
In Proceedings of the IEEE Annual Symposium on VLSI, Kefalonia,
Greece, July 2010.
[ bib |
.pdf ]
|
|
[52]
|
Bernard Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos,
Sotirios Xydis, Alexandros Bartzas, Dimitris Bekiaris, Dimitrios Soudris,
Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, Ahmed Hemani, Axel Jantsch,
Geert Vanmeerbeeck, Jari Kreku, Kari Tiensyrja, Fragkiskos Ieromnimon,
Dimitrios Kritharidis, Andreas Wiefrink, Bart Vanthournout, and Philippe
Martin.
Mapping Optimisation for Scalable multi-core ARchiTecture:
The MOSART approach.
In Proceedings of the IEEE Annual Symposium on VLSI, Kefalonia,
Greece, July 2010.
[ bib |
.pdf ]
|
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[53]
|
Abdul Naeem, Xiaowen Chen, Zhonghai Lu, and Axel Jantsch.
Scalability of Weak Consistency in NoC based Multicore
Architectures.
In Proceedings of the IEEE International Symposium on Circuits
and Systems (ISCAS), Paris, France, June 2010.
[ bib |
.pdf ]
|
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[54]
|
Amr Helmy, Laurence Pierre, and Axel Jantsch.
Theorem Proving Techniques for Formal Verification of NoC
Communications with Non-minimal Adaptive Routing.
In Proceedings of the 13th IEEE International Symposium on
Design & Diagnostics of Electronic Circuits & Systems, Vienna, Austria,
April 2010.
[ bib |
.pdf ]
|
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[55]
|
Fahimeh Jafari, Zhonghai Lu, Axel Jantsch, and Mohammad H. Yaghmaee.
Optimal Regulation of Traffic Flows in Networks-on-Chip.
In Proceedings of the Design Automation and Test Europe
Conference (DATE), Dresden, March 2010.
[ bib |
.pdf ]
|
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[56]
|
Xiaowen Chen, Zhonghai Lu, Axel Jantsch, and Shuming Chen.
Supporting Distributed Shared Memory on Multi-core
Network-on-Chips Using a Dual Microcoded Controller.
In Proceedings of the confernece for Design Automation and Test
in Europe, Dresden, Germany, March 2010.
[ bib |
.pdf ]
|
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[57]
|
Abdul Naeem, Xiaowen Chen, Zhonghai Lu, and Axel Jantsch.
Scalability of Transaction Counter based Relaxed Consistency
Models in NoC based Multicore Architectures.
ACM SIGARCH Computer Architecture News, December 2009.
[ bib |
.pdf ]
|
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[58]
|
Zhonghai Lu and Axel Jantsch.
Trends of Terascale Computing Chips in the Next Ten Years.
In Proceedings of IEEE ASICON 2009, ChangSha, China, October
2009.
[ bib |
http ]
|
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[59]
|
Xiaowen Chen, Zhonghai Lu, Axel Jantsch, and Shuming Chen.
Speedup Analysis of Data-parallel Applications on Multi-core
NoCs.
In Proceedings of the IEEE International Conference on ASIC
(ASICON), Changsha, China, October 2009.
[ bib |
.pdf ]
|
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[60]
|
Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa, Zhonghai Lu, Axel Jantsch,
Roshan Weerasekera, and Hannu Tenhunen.
Scalability of Network-on-Chip Communication Architecture for
3-D Meshes.
In Proceedings of the International Symposium on
Networks-on-Chip, San Diego, CA, May 2009.
[ bib |
.pdf ]
|
|
[61]
|
Yuang Zhang, Zhonghai Lu, Axel Jantsch, Li Li, and Minglun Gao.
Towards Hierarchical Cluster based Cache Coherence for
Large-Scale Network-on-Chip.
In Proceedings of the 4th IEEE International Conference on
Design & Technology of Integrated Systems in Nanoscale Era, Cairo, Egypt,
April 2009.
[ bib |
.pdf ]
|
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[62]
|
Mikael Millberg and Axel Jantsch.
Priority Based Forced Requeue to Reduce Worst-Case Latency
for Bursty Traffic.
In Proceedings of the Design Automation and Test Europe
Conference (DATE), April 2009.
[ bib |
.pdf ]
|
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[63]
|
Zhonghai Lu, Mikael Millberg, Axel Jantsch, Alistair Bruce, Pieter van der
Wolf, and Tomas Henriksson.
Flow Regulation for On-Chip Communication.
In Proceedings of the Design Automation and Test Europe
Conference (DATE), April 2009.
[ bib |
.pdf ]
|
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[64]
|
Zhonghai Lu, Dimitris Brachos, and Axel Jantsch.
A Flow Regulator for On-Chip Communication.
In Proceedings of the System on Chip Conference, Belfast,
Northern Ireland, 2009.
[ bib |
.pdf ]
|
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[65]
|
Axel Jantsch and Zhonghai Lu.
Resource Allocation for Quality of Service in On-Chip
Communication.
In Fayez Gebali and Haytham Elmiligi, editors, Networks on Chip:
Theory and Practice. Taylor & Francis Group LLC - CRC Press, 2009.
[ bib |
.pdf ]
|
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[66]
|
Zhonghai Lu, Axel Jantsch, Erno Salminen, and Cristian Grecu.
Network-on Chip Micro-Benchmarks.
Embedded Systems Design, September 2008.
[ bib |
http ]
|
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[67]
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Zhonghai Lu and Axel Jantsch.
TDM Virtual-Circuit Configuration for Network-on-Chip.
IEEE Transactions on Very Large Scale Integration Systems,
16(8), August 2008.
[ bib |
.pdf ]
|
|
[68]
|
Zhonghai Lu, Lei Xia, and Axel Jantsch.
Cluster-based Simulated Annealing for Mapping Cores onto 2D
Mesh Networks on Chip.
In Proceedings of the IEEE Workshop on Design and Diagnostics of
Electronic Circuits and Systems, April 2008.
[ bib |
.pdf ]
|
|
[69]
|
Arseni Vitkovski, Axel Jantsch, Robert Lauter, Raimo Haukilahti, and Erland
Nilsson.
Low-pwer and error protection coding for Network-on-Chip
traffic.
IET Computers and Digital Techniques, 2(6):483--492, 2008.
[ bib |
.pdf ]
|
|
[70]
|
Zhonghai Lu and Axel Jantsch.
Slot Allocation Using Logical Networks for TDM
Virtual-Circuit Configuration for Network-on-Chip.
In International Conference on Computer Aided Design (ICCAD),
November 2007.
[ bib |
.pdf ]
|
|
[71]
|
Zhonghai Lu and Axel Jantsch.
Admitting and Ejecting Flits in Wormhole-switched Networks on
Chip.
IET Computers & Digital Techniques, 5(1):546--556, September
2007.
[ bib ]
|
|
[72]
|
Iyad Al-Khatib, Davide Bertozzi, Axel Jantsch, and Luca Benini.
Performance Analysis and Design Space Exploration for
High-End Biomedical Applications: Challenges and Solutions.
In Proceedings of the International Conference on Hardware -
Software Codesign and System Synthesis, September 2007.
[ bib |
.pdf ]
|
|
[73]
|
Mickael Millberg and Axel Jantsch.
Increasing NoC Performance and Utilisation using a
DualPacket Exit Strategy.
In 10th Euromicro Conference on Digital System Design, Lubeck,
Germany, August 2007.
[ bib |
.pdf ]
|
|
[74]
|
Zhonghai Lu, Ming Liu, and Axel Jantsch.
Layered Switching for Networks on Chip.
In Proceedings of the Design Automation Conference, June 2007.
[ bib |
.pdf ]
|
|
[75]
|
Mickael Millberg and Axel Jantsch.
Improvements of Performance and Use of Buffers in NoCs
using Dual Packet Exit.
In Proceedings of the 1st Symposium on Networks on Chip, May
2007.
poster.
[ bib |
.pdf ]
|
|
[76]
|
Andre Ivanov Cristian Grecu and, Partha Pande, Axel Jantsch, Erno Salminen,
Umit Ogras, and Radu Marculescu.
Towards open network-on-chip benchmarks.
In Proceedings of First International Symposium on
Networks-on-Chip, May 2007.
[ bib |
.pdf ]
|
|
[77]
|
Per Badlund and Axel Jantsch.
An analytical approach for dimensioning mixed traffic
networks.
In Proceedings of the 1st Symposium on Networks on Chip, May
2007.
poster.
[ bib |
.pdf ]
|
|
[78]
|
Rikard Thid, Ingo Sander, and Axel Jantsch.
Flexible Bus and NoC Performance Analysis with Configurable
Synthetic Workloads.
In 9th Euromicro Conference on Digital System Design (DSD
2006), August 2006.
[ bib |
.pdf ]
|
|
[79]
|
Sandro Penolazzi and Axel Jantsch.
A High Level Power Model for the Nostrum NoC.
In 9th Euromicro Conference on Digital System Design (DSD
2006), August 2006.
[ bib |
.pdf ]
|
|
[80]
|
Zhonghai Lu, Ingo Sander, and Axel Jantsch.
Towards Performance-oriented Pattern-based Refinement of
Synchronous Models onto NoC Communication.
In 9th Euromicro Conference on Digital System Design (DSD
2006), August 2006.
[ bib |
.pdf ]
|
|
[81]
|
Liang Guang and Axel Jantsch.
Adaptive Power Management for the On-Chip Communication
Network.
In 9th Euromicro Conference on Digital System Design (DSD),
August 2006.
[ bib |
.pdf ]
|
|
[82]
|
Axel Jantsch.
Models of Computation for Networks on Chip.
In Proceedings of the Sixth International Conference on
Application of Concurrency to System Design, June 2006.
invited paper.
[ bib |
.pdf ]
|
|
[83]
|
Zhonghai Lu, Bei Yin, and Axel Jantsch.
Connection-oriented Multicasting in Wormhole-switched
Networks on Chip.
In Proceedings of the IEEE Computer Society Annual Symposium on
VLSI, March 2006.
[ bib |
.pdf ]
|
|
[84]
|
Zhonghai Lu, Mingchen Zhong, and Axel Jantsch.
Evaluation of Onchip Networks Using Deflection Routing.
In Proceedings of GLSVLSI, 2006.
[ bib |
.pdf ]
|
|
[85]
|
Zhonghai Lu, Ingo Sander, and Axel Jantsch.
Refining Synchronous Communication onto Network-on-Chip
Best-effort Services.
In Alain Vachoux, editor, Advances in Design and Specification
Languages for SoCs - Selected Contributions from FDL 2005. Springer
Verlag, 2006.
[ bib |
.pdf ]
|
|
[86]
|
Iyad Al Khatib, Davide Bertozzi, Francesco Poletti, Luca Benini, Axel Jantsch,
Mohamed Bechara, Hasan Khalifeh, Mazen Hajjar, Rustam Nabiev, and Sven
Jonsson.
MPSoC ECG Biochip: A Multiprocessor System-on-Chip
for Real-Time Human Heart Monitoring and Analysis.
In Proceedings of the ACM Computing Frontiers, 2006.
[ bib |
.pdf ]
|
|
[87]
|
Zhonghai Lu, Ingo Sander, and Axel Jantsch.
Refinement of A Perfectly Synchronous Communication Model
onto Nostrum NoC Best-Effort Communication.
In Proceedings of the Forum on Design Languages, September
2005.
[ bib |
.pdf ]
|
|
[88]
|
Zhonghai Lu, Li Tong, Bei Yin, and Axel Jantsch.
A power efficient flit-admission scheme for wormhole-switched
networks on chip.
In Proceedings of the 9th World Multi-Conference on Systemics,
Cybernetics and Informatics, July 2005.
[ bib |
.pdf ]
|
|
[89]
|
Zhonghai Lu and Axel Jantsch.
Traffic Configuration for Evaluating Networks on Chips.
In Proceedings of the 5th International Workshop on Systems on
Chip (IWSOC), July 2005.
[ bib |
.pdf ]
|
|
[90]
|
Iyad Al Khatib, Axel Jantsch, Bassam Kayal, Rustam Nabiev, and Sven Jonsson.
Wireless Network-on-Chips as Autonomous Systems: A Novel
Solution for Biomedical Healthcare and Space Exploration Sensor-Networks.
In Proceedings of the Infocom 2005 Conference - Student
Workshop, March 2005.
[ bib |
.pdf ]
|
|
[91]
|
Zhonghai Lu, Axel Jantsch, and Ingo Sander.
Feasibility Analysis of Messages for On-chip Networks Using
Wormhole Routing.
In Proceedings of the Asian Pacific Design Automation
Conference, 2005.
[ bib |
.pdf ]
|
|
[92]
|
Iyad Al Khatib, Axel Jantsch, and Mohammad Saleh.
Simulation of Real Home Healthcare Sensor Networks Utilizing
IEEE 802.11g Biomedical Network-on-Chip.
In Proceedings of REALWAN, Stockholm, 2005.
[ bib ]
|
|
[93]
|
Axel Jantsch, Robert Lauter, and Arseni Vitkowski.
Power analysis of link level and end-to-end data protection
on networks on chip.
In Proceedings of the IEEE International Symposium on Circuits
and Systems, 2005.
[ bib |
.pdf ]
|
|
[94]
|
Arseni Vitkovski, Raimo Haukilahti, Axel Jantsch, and Erland Nilsson.
Low-Power and Error Coding for Network-on-Chip Traffic.
In Proceedings of the IEEE NorChip Conference, November 2004.
[ bib |
.pdf ]
|
|
[95]
|
Zhonghai Lu and Axel Jantsch.
Flit Ejection in On-chip Wormhole-switched Networks with
Virtual Channels.
In Proceedings of the IEEE NorChip Conference, November 2004.
[ bib |
.pdf ]
|
|
[96]
|
Zhonghai Lu and Axel Jantsch.
Flit Admission in On-chip Wormhole-switched Networks with
Virtual Channels.
In Proceedings of the International Symposium on System-on-Chip
2003, November 2004.
[ bib |
.pdf ]
|
|
[97]
|
Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch,
and Hannu Tenhunen.
A Study on the Implementation of 2-D Mesh based Networks on
Chip in the Nanoregime.
Integration - The VLSI Journal, 38(1):3--17, October 2004.
[ bib ]
|
|
[98]
|
Heiko Zimmer and Axel Jantsch.
Error-tolerant Interconnect Schemes.
In Jari Nurmi, Hannu Tenhunen, Jouni Isoaho, and Axel Jantsch,
editors, Interconnect-Centric Design for Advanced SoCs and NoCs,
chapter 6. Kluwer Academic Publisher, April 2004.
[ bib |
.pdf ]
|
|
[99]
|
Mikael Millberg, Erland Nilsson, Rikard Thid, and Axel Jantsch.
Guaranteed Bandwidth using Looped Containers in Temporally
Disjoint Networks within the Nostrum Network on Chip.
In Proceedings of the Design Automation and Test Europe
Conference (DATE), February 2004.
[ bib |
.pdf ]
|
|
[100]
|
Axel Jantsch, Johnny Öberg, and Hannu Tenhunen.
Special Issue on Networks on Chip - guest editor's
introduction.
Journal of Systems Architecture, 50(2-3), February 2004.
[ bib |
.pdf ]
|
|
[101]
|
Mikael Millberg, Erland Nilsson, Rikard Thid, Shashi Kumar, and Axel Jantsch.
The Nostrum Backbone - a Communication Protocol Stack for
Networks on Chip.
In Proceedings of the VLSI Design Conference, Mumbai, India,
January 2004.
[ bib |
.pdf ]
|
|
[102]
|
D. Pamunuwa, J. Öberg, L. R. Zheng, M. Millberg, A. Jantsch, and H. Tenhunen.
Layout, Performance and Power Trade-Offs in Mesh-Based
Network-on-Chip Architectures.
In IFIP International Conference on Very Large Scale Integration
(VLSI-SOC), Darmstadt, Germany, December 2003.
[ bib |
.pdf ]
|
|
[103]
|
Richard Thid, Mikael Millberg, and Axel Jantsch.
Evaluating NoC communication backbones with simulation.
In Proceedings of the IEEE NorChip Conference, November 2003.
[ bib |
.pdf ]
|
|
[104]
|
Heiko Zimmer and Axel Jantsch.
A Fault Model Notation and Error-Control Scheme for
Switch-to-Switch Buses in a Network-on-Chip.
In Proceedings of the CODES-ISSS Conference, October 2003.
[ bib |
.pdf ]
|
|
[105]
|
Axel Jantsch.
NoCs: A new Contract between Hardware and Software.
In Proceedings of the Euromicro Symposium on Digital System
Design, September 2003.
Invited keynote.
[ bib |
.pdf ]
|
|
[106]
|
Erland Nilsson, Mikael Millberg, Johnny Öberg, and Axel Jantsch.
Load distribution with the Proximity Congestion Awareness in
a Network on Chip.
In Proceedings of the Design Automation and Test Europe (DATE),
pages 1126--1127, March 2003.
[ bib |
.pdf ]
|
|
[107]
|
Axel Jantsch and Hannu Tenhunen, editors.
Networks on Chip.
Kluwer Academic Publishers, February 2003.
[ bib |
http ]
|
|
[108]
|
Axel Jantsch and Hannu Tenhunen.
Will Networks on Chip Close the Productivity Gap?
In Axel Jantsch and Hannu Tenhunen, editors, Networks on Chip,
chapter 1, pages 3--18. Kluwer Academic Publishers, February 2003.
[ bib |
.pdf ]
|
|
[109]
|
Yi-Ran Sun, Shashi Kumar, and Axel Jantsch.
Simulation and Evaluation of a Network on Chip Architecture
Using Ns-2.
In Proceedings of the IEEE NorChip Conference, November 2002.
[ bib ]
|
|
[110]
|
Axel Jantsch.
Network on Chip.
In Proceedings of the Conference Radio vetenskap och
Kommunication, Stockholm, June 2002.
[ bib |
.pdf ]
|
|
[111]
|
Shashi Kumar, Axel Jantsch, Juha-Pekka Soininen, Martti Forsell, Mikael
Millberg, Johnny Öberg, Kari Tiensyrjä, and Ahmed Hemani.
A Network on Chip Architecture and Design Methodology.
In Proceedings of IEEE Computer Society Annual Symposium on
VLSI, April 2002.
[ bib |
.pdf ]
|
|
[112]
|
Axel Jantsch, Juha-Pekka Soininen, Martti Forsell, Li-Rong Zheng, Shashi Kumar,
Mikael Millberg, and Johnny Öberg.
Networks on Chip.
In Workshop at the European Solid State Circuits Conference,
September 2001.
[ bib ]
|
|
[113]
|
Ahmed Hemani, Axel Jantsch, Shashi Kumar, Adam Postula, Johnny Öberg, Mikael
Millberg, and Dan Lindqvist.
Network on Chip: An architecture for billion transistor era.
In Proceeding of the IEEE NorChip Conference, November 2000.
[ bib |
.pdf ]
|
|
[1]
|
Sofia Maragkou, Miltos Grammatikakis, Nikos Papatheodorou, and Axel Jantsch.
Secure Authentication in the Presence of Malicious Messages
and Packet Reorders: Study on CAN Bus.
In 2025 IEEE 15th Annual Computing and Communication Workshop
and Conference (CCWC), pages 00952--00959, 2025.
[ bib |
DOI |
.pdf ]
|
|
[2]
|
Florian Egert, Sofia Maragkou, Markus Kobelrausch, Bernhard Fischer, and Axel
Jantsch.
A Methodology for Automating the Integration of User-Defined
Instructions into RISC-V Systems based on the CV-X-IF Interface.
In RISC-V Summit Europe, Munich, Germany, June 2024.
[ bib |
.pdf ]
|
|
[3]
|
Axel Jantsch, Swaroop Ghosh, Umit Ogras, and Pascal Meinerzhagen.
ISLPED 2023: International Symposium on Low-Power Electronics
and Design.
IEEE Design & Test, 41(1):93--94, 2024.
[ bib |
DOI ]
|
|
[4]
|
Matthias Bittner, Dominik Dallinger, Matthias Wess Daniel Schnöll,
Maximilian Götzinger, and Axel Jantsch.
Once-For-All Neural Architecture for Time Series
Classification on Microcontroller Platforms.
In Under submission, 2024.
[ bib ]
|
|
[5]
|
Muhammad Noman Sohail, Adeel Anjum, Iftikhar Ahmed Saeed, Madiha Haider Syed,
Axel Jantsch, and Semeen Rehman.
Optimizing Industrial IoT Data Security through
Blockchain-Enabled Incentive-Driven Game Theoretic Approach for Data
Sharing.
IEEE Access, pages 1--1, 2024.
[ bib |
DOI |
.pdf ]
|
|
[6]
|
Alireza Estaji, Maximilian Götzinger, Benedikt Tutzer, Stefan Kollmann,
Thilo Sauter, and Axel Jantsch.
Evaluation of Drift Detection Algorithms in the Condition
Monitoring Domain.
IEEE Transactions on Industrial Informatics, pages 1--10, 2024.
[ bib |
DOI |
.pdf ]
|
|
[7]
|
Istvan Andras Gergely, Sebastian Rausch, Nahla Elaraby, and Axel Jantsch.
Resource Management of Automotive Engine Control Units.
In 2024 IFIP/IEEE 32nd International Conference on Very Large
Scale Integration (VLSI-SoC), pages 1--4, 2024.
[ bib |
DOI ]
|
|
[8]
|
Maryna Kolisnyk and Axel Jantsch.
ML-based Fault Tree Analysis of Industrial Router Reliability
in the System IIoT.
In 2024 International Conference on Applied Mathematics &
Computer Science (ICAMCS), pages 173--178, 2024.
[ bib |
DOI ]
|
|
[9]
|
Saeed Seyedfaraji, Salar Shakibhamedan, Amire Seyedfaraji, Baset Mesgari, Nima
TaheriNejad, Axel Jantsch, and Semeen Rehman.
E-MAC: Enhanced In-SRAM MAC Accuracy via Digital-to-Time
Modulation.
IEEE Journal on Exploratory Solid-State Computational Devices
and Circuits, pages 1--1, 2024.
[ bib |
DOI |
.pdf ]
|
|
[10]
|
Salar Shakibhamedan, Anice Jahanjoo, Amin Aminifar, Nima Amirafshar, Nima
TaheriNejad, and Axel Jantsch.
An Analytical Approach to Enhancing DNN Efficiency and
Accuracy Using Approximate Multiplication.
In 2nd Workshop on Advancing Neural Network Training:
Computational Efficiency, Scalability, and Resource Optimization (WANT@ICML
2024), 2024.
[ bib |
http ]
|
|
[11]
|
Axel Jantsch.
Taking AIMS at Digital Design - Analysis, Improvement,
Modeling, and Synthesis.
Springer, May 2023.
[ bib |
DOI |
http ]
|
|
[12]
|
Maryna Kolisnyk, Axel Jantsch, Tanja Zseby, and Vyacheslav Kharchenko.
Markov Model of PLC Availability Considering Cyber-Attacks
in Industrial IoT.
In Coen van Gulijk, Elena Zaitseva, and Miroslav Kvassay, editors,
Reliability Engineering and Computational Intelligence for Complex
Systems, volume 496 of Studies in Systems, Decision and Contro, pages
61--78. Springer, Leiden, The Netherlands, 2023.
[ bib |
DOI |
www: ]
|
|
[13]
|
Nahla El-Araby and Axel Jantsch.
Reliable Power Efficient Systems through Run-time
Reconfiguration.
In Proceedings of the IEEE International NEWCAS Conference,
Quebec, Canada, June 2022.
[ bib |
.pdf ]
|
|
[14]
|
Mojtaba Valinataj and Axel Jantsch.
Hierarchical multipliers: A framework for high-speed multiple
error detecting architectures.
Microelectronics Journal, page 105459, 2022.
[ bib |
DOI |
http ]
The demand for high-performance and reliable
processing systems is steadily increasing, also in
applications where multiple transient faults may
occur. As multipliers are one of the main building
blocks of the processing systems, employing a
cost-efficient and high-speed method handling
multiple-errors is of great importance. In this
paper, at first a framework to achieve multiple
error detection in the multipliers is proposed,
which is entirely independent of the multiplier type
and error detection method. Then, the self-checking
hierarchical multipliers with multiple error
detection capability up to the size of 64 × 64 bits
are proposed in such a way that the low-cost and
high-speed designs are achieved with high multiple
error detection probabilities. Experimental results
based on analysis and simulation show that the
proposed 32 × 32 and 64 × 64 multipliers based on
each of Dadda or Braum structures as high-speed
parallel and array multipliers, respectively,
achieve more than 99.8 against three or more simultaneous errors. This
capability for 64 × 64 multipliers is attained with
35 compared to the basic non-self-checking design.
|
|
[15]
|
Nahla El-Araby, David Frismuth, Nilson Neves Filho, and Axel Jantsch.
Run Time Power and Accuracy Management with Approximate
Circuits.
In International Conference on Very Large Scale Integration
(VLSI-SoC), 2022.
[ bib |
DOI ]
|
|
[16]
|
Maryna Kolisnyk, Axel Jantsch, and Iryna Piskachova.
Markov Model for Availability Assessment of PLC in Industrial
IoT Considering Subsystems Failures.
In 2022 12th International Conference on Dependable Systems,
Services and Technologies (DESSERT), pages 1--4, 2022.
[ bib |
DOI ]
|
|
[17]
|
Yassmeen Elderhalli, Nahla El-Araby, Osman Hasan, Axel Jantsch, and Sofiene
Tahar.
Dynamic Fault Tree Models for FPGA Fault Tolerance and
Reliability.
In Proceedings of the IEEE Computer Society Annual Symposium on
VLSI (ISVLSI), Tampa, Florida, USA, July 2021.
[ bib |
.pdf ]
|
|
[18]
|
Dávid Juhász and Axel Jantsch.
Dynamic Constraints for Mixed-Criticality Systems.
In International Conference on Omni-layer Intelligent systems
(COINS), Crete, Greece, May 2019.
[ bib |
.pdf ]
|
|
[19]
|
Sina Shahhosseini, Iman Azimi, Arman Anzanpour, Axel Jantsch, Pasi Liljeberg,
Nikil Dutt, and Amir M. Rahmani.
Dynamic Computation Migration at the Edge: Is There an
Optimal Choice?
In Proceedings of the Great Lake Symposium on VLSI (GLSVLS),
Washington DC, USA, May 2019. ACM.
[ bib |
DOI |
.pdf ]
|
|
[20]
|
Martin Mosbeck, Daniel Hauer, and Axel Jantsch.
VELS: VHDL E-Learning System for Automatic Generation
and Evaluation of Per-Student Randomized Assignments.
In IEEE Nordic Circuits and Systems Conference (NorCAS),
Tallinn, Estonia, October 2018.
[ bib |
.pdf ]
|
|
[21]
|
Robin Arbaud, Dávid Juhász, and Axel Jantsch.
Management of Resources for Mixed-Critical Systems on
Multi-Core Platforms with explicit consideration of Communication.
In Proceedings of the Euromicro Conference on Digital System
Design (DSD), September 2018.
invited tutorial.
[ bib |
.pdf ]
|
|
[22]
|
Dávid Juhász and Axel Jantsch.
Addressing the Execution Control Problem in Mixed-Criticality
Systems.
In Proceedings of the Euromicro Conference on Digital System
Design (DSD), Prague, Czech Republic, September 2018.
Work in Progress.
[ bib |
.pdf ]
|
|
[23]
|
Amir M. Rahmani, Bryan Donyanavard, Tiago Mück, Kasra Moazzemi, Axel Jantsch,
Onur Mutlu, and Nikil Dutt.
SPECTR - Formal Supervisory Control and Coordination for
Many-core Systems Resource Management.
In Proceedings of the 23rd ACM International Conference on
Architectural Support for Programming Languages and Operating Systems,
Williamsburg, VA, USA, March 2018.
[ bib |
.pdf ]
|
|
[24]
|
Axel Jantsch, Arman Anzanpour, Hedyeh Kolerdi, Iman Azimi, Lydia Chaido
Siafara, Amir M. Rahmani, Nima TaheriNejad, Pasi Liljeberg, and Nikil Dutt.
Hierarchical Dynamic Goal Management for IoT Systems.
In Proceedings of the IEEE International Symposium on Quality
Electronic Design (ISQED 2018), USA, March 2018.
[ bib |
.pdf ]
|
|
[25]
|
Amir Rahmani, Pasi Liljeberg, Jürgo-Sören Preden, and Axel Jantsch,
editors.
Fog Computing in the Internet of Things.
Springer, 2018.
[ bib ]
|
|
[26]
|
Kalle Tammemäe, Axel Jantsch, Alar Kuusik, Jürgo-Sören Preden, and
Enn Ounapuu.
Self-Aware Fog Computing in Private and Secure Spheres.
In Amir M. Rahmani, Pasi Liljeberg, Jürgo-Sören Preden, and
Axel Jantsch, editors, Fog Computing in the Internet of Things -
Intelligence at the Edge. Springer, 2018.
[ bib |
.pdf ]
|
|
[27]
|
Behailu Negash, Amir M. Rahmani, Pasi Liljeberg, and Axel Jantsch.
Fog Computing Fundamentals in The Internet-of-Things.
In Amir M. Rahmani, Pasi Liljeberg, Jürgo-Sören Preden, and
Axel Jantsch, editors, Fog Computing in the Internet of Things -
Intelligence at the Edge, chapter 1. Springer, 2018.
[ bib |
.pdf ]
|
|
[28]
|
T. R. Mück, B. Donyanavard, K. Moazzemi, A. M. Rahmani, A. Jantsch, and N. D.
Dutt.
Design Methodology for Responsive and Robust MIMO Control
of Heterogeneous Multicores.
IEEE Transactions on Multi-Scale Computing Systems,
PP(99):1--1, 2018.
[ bib |
DOI |
.pdf ]
|
|
[29]
|
Anil Kanduri, Mohammad-Hashem Haghbayan, Amir M. Rahmani, Muhammad Shafique,
Axel Jantsch, and Pasi Liljeberg.
adBoost: Thermal Aware Performance Boosting through Dark
Silicon Patterning.
IEEE Transactions on Computers, 2018.
[ bib |
DOI |
.pdf ]
|
|
[30]
|
Axel Jantsch.
Darf ich meinen Haushaltsroboter foltern?
Profil, (19. April), 2018.
[ bib |
.pdf ]
|
|
[31]
|
Sai Manoj Pudukotai Dinakarrao and Axel Jantsch.
ADDHard: Arrhythmia Detection with Digital Hardware by
Learning ECG Signal.
In Proceedings of the Great Lake Symposium on VLSI, pages
495--498, 2018.
[ bib |
.pdf ]
|
|
[32]
|
Anil Kanduri, Mohammad-Hashem Haghbayan, Amir M. Rahmani, Pasi Liljeberg, Axel
Jantsch, Hannu Tenhunen, and Nikil Dutt.
Accuracy Aware Power Management for Many-core Systems running
Error Resilient Applications.
IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, 25(10), October 2017.
[ bib |
DOI ]
|
|
[33]
|
Junshi Wang, Masoumeh Ebrahimi, Letian Huang, Qiang Li, Guangjun Li, and Axel
Jantsch.
Minimizing the System Impact of Router Faults by Means of
Reconfiguration and Adaptive Routing.
Microprocessors and Microsystems, 51:252 -- 263, June 2017.
[ bib |
DOI |
http ]
|
|
[34]
|
Carna Radojicic, Christoph Grimm, Axel Jantsch, and Michael Rathmair.
Towards Verification of Uncertain Cyber-Physical Systems.
In Erika Ábrahám and Sergiy Bogomolov, editors,
Proceedings 3rd International Workshop on Symbolic and Numerical Methods for
Reachability Analysis, Uppsala, Sweden, 22nd April 2017, volume 247 of
Electronic Proceedings in Theoretical Computer Science, pages 1--17. Open
Publishing Association, June 2017.
[ bib |
DOI |
.pdf ]
|
|
[35]
|
M. H. Haghbayan, A. M. Rahmani, P. Liljeberg, A. Jantsch, A. Miele,
C. Bolchini, and H. Tenhunen.
Can Dark Silicon Be Exploited to Prolong System Lifetime?
IEEE Design Test, 34(2):51--59, April 2017.
[ bib |
DOI |
.pdf ]
|
|
[36]
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A. M. Rahmani, M. H. Haghbayan, A. Miele, P. Liljeberg, A. Jantsch, and
H. Tenhunen.
Reliability-Aware Runtime Power Management for Many-Core
Systems in the Dark Silicon Era.
IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, 25(2):427--440, February 2017.
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[37]
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Anil Kanduri, Mohammad-Hashem Haghbayan, Amir M. Rahmani, Pasi Liljeberg, Axel
Jantsch, Nikil Dutt, and Hannu Tenhunen.
Approximation Knob: Power Capping Meets Energy Efficiency.
In Proceedings of the International Conference on Computer Aided
Design (ICCAD), Austin, Texas, November 2016.
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Junshi Wang, Letian Huang, Qiang Li, Guangjun Li, and Axel Jantsch.
Optimizing the Location of ECC Protection in
Network-on-Chip.
In Proceeding of the International Conference on
Hardware/Software Codesign and System Synthesis (CODES+ISSS), Pittsburgh,
October 2016.
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[39]
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Nima TaheriNejad, Sai Manoj P. D., Michael Rathmair, and Axel Jantsch.
Fully Digital Write-in Scheme for Multi-Bit Memristive
Storage.
In 13th International Conference on Electrical Engineering,
Computing Science and Automatic Control (CCE 2016), Mexico, September 2016.
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.pdf ]
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Junshi Wang, Letian Huang, Guangjun Li, and Axel Jantsch.
Calculation of delivery rate in fault-tolerant
network-on-chips.
Electronics Letters, March 2016.
[ bib |
DOI |
.pdf ]
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[41]
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Amir Mohammad Rahmani, Pasi Liljeberg, Ahmed Hemani, Axel Jantsch, and Hannu
Tenhunen, editors.
The Dark Side of Silicon.
Springer, 2016.
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[42]
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Junshi Wang, Yang Huang, Masoumeh Ebrahimi, Letian Huang, Qiang Li, Axel
Jantsch, and Guangjun Li.
VisualNoC: A Visualization and Evaluation Environment for
Simulation and Mapping.
In Proceedings of the Third ACM International Workshop on
Many-core Embedded Systems, MES '16, pages 18--25, New York, NY, USA, 2016.
ACM.
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[43]
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Amir M. Rahmani, Mohammad-Hashem Haghbayan, Pasi Liljeberg, Axel Jantsch, and
Hannu Tenhunen.
Multi-Objective Power Management for CMPs in the Dark
Silicon Age.
In Amir M. Rahmani, Pasi Liljeberg, Ahmed Hemani, Axel Jantsch, and
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Anil Kanduri, Amir M. Rahmani, Pasi Liljeberg, Ahmed Hemani, Axel Jantsch, and
Hannu Tenhunen.
Dark Silicon - Challenges and Opportunities.
In Amir M. Rahmani, Pasi Liljeberg, Ahmed Hemani, Axel Jantsch, and
Hannu Tenhunen, editors, The Dark Side of Silicon, chapter 1. Springer,
2016.
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Anil Kanduri, Mohammad-Hashem Haghbayan, Amir M. Rahmani, Pasi Liljeberg, Axel
Jantsch, and Hannu Tenhunen.
Dark Silicon Patterning: Efficient Power Utilization through
Run-time Mapping.
In Amir M. Rahmani, Pasi Liljeberg, Ahmed Hemani, Axel Jantsch, and
Hannu Tenhunen, editors, The Dark Side of Silicon, chapter 9. Springer,
2016.
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[46]
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Letian Huang, Junshi Wang, Masoumeh Ebrahimi, Masoud Daneshtalab, Xiaofan
Zhang, Guangjun Li, and Axel Jantsch.
Non-blocking Testing for Network-on-Chip.
IEEE Transactions on Computers, 65(3):679--692, 2016.
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DOI |
http ]
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[47]
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Anil Kanduri, Mohammad-Hashem Haghbayan, Amir-Mohammad Rahmani, Pasi Liljeberg,
Axel Jantsch, and Hannu Tenhunen.
Dark Silicon Aware Runtime Mapping for Many-core Systems: A
Patterning Approach.
In Proceedings of the International Conference on Computer
Design (ICCD), pages 610--617, New York City, USA, October 2015.
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Mohammad-Hashem Haghbayan, Anil Kanduri, Amir-Mohammad Rahmani, Pasi Liljeberg,
Axel Jantsch, and Hannu Tenhunen.
MapPro: Proactive Runtime Mapping for Dynamic Workloads by
Quantifying Ripple Effect of Applications on Networks-on-Chip.
In Proceedings of the International Symposium on Networks on
Chip, Vancouver, Canada, September 2015.
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Andreas Steininger, Horst Zimmermann, Axel Jantsch, Michael Hofbauer, Ulrich
Schmid, Kurt Schweiger, and Varadan Savulimedu Veeravalli.
Building reliable systems-on-chip in nanoscale technologies.
Elektrotechnik & Informationstechnik, 132(6):301--306, August
2015.
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.pdf ]
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Junshi Wang, Masoumeh Ebrahimi, Letian Huang, Axel Jantsch, and Guangjun Li.
Design of Fault-Tolerant and Reliable Networks-on-Chip.
In IEEE Annual Symposium on VLSI (ISVLSI), Montpelllier,
France, July 2015.
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Amirmohammad Rahmani, Hannu Tenhunen, Pasi Liljeberg, Awet Yemane Weldezion,
Srinivasa Kanduru, Juha Plosila, Mohammadhashem Haghbayan, and Axel Jantsch.
Dynamic Power Management for Many-Core Platforms in the Dark
Silicon Era: A Multi-Objective Control Approach.
In Proceedings of the International Symposium on Low Power
Electronics and Design, Rome, Italy, July 2015.
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[52]
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Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Yang Li, Shuming Chen, Yang Guo,
Zonglin Liu, Jianghua Wan, Jianzhuang Lu, Shuwei Sun, Shenggang Chen,
Hu Chen, and Man Liao.
Achieving Memory Access Equalization via Round-trip Routing
Latency Prediction in 3D Many-core.
In IEEE Annual Symposium on VLSI (ISVLSI), Montpelllier,
France, July 2015.
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[53]
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Xiaofan Zhang, Masoumeh Ebrahimi, Letian Huang, Guangjun Li, and Axel Jantsch.
A Network-Level Solution for Fault Detection, Masking, and
Tolerance in NoCs.
In Proceedings of 23rd IEEE Euromicro Conference on Parallel,
Distributed and Network-Based Computing, (PDP), Finland, March 2015.
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[54]
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Yuang Zhang, Li Li, Axel Jantsch, Zhonghai Lu, Minglun Gao, Yuxiang Fu, and
Hongbing Pan.
Exploring Stacked Main Memory Architecture for 3D
GPGPUs.
In IEEE International Conference on ASIC (ASICON), Chengdu,
China, 2015.
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[55]
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Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Yang Guo, Shenggang
Chen, and Hu Chen.
Performance Analysis of Homogeneous On-chip Large-scale
Parallel Computing Architectures for Data-parallel Applications.
Journal of Electrical and Computer Engineering, 2015.
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DOI |
.pdf ]
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[56]
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Mohammad-Hashem Haghbayan, Amir-Mohammad Rahmani, Awet Yemane Weldezion, Pasi
Liljeberg, Juha Plosila, Axel Jantsch, and Hannu Tenhunen.
Dark Silicon Aware Power Management for Manycore Systems
under Dynamic Workloads.
In Proceedings of the International Conference on Computer
Design, Seoul, South Korea, October 2014.
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[57]
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Masoumeh Ebrahimi, Junshi Wang, Letian Huang, Masoud Daneshtalab, and Axel
Jantsch.
Rescuing Healthy Cores Against Disabled Routers.
In Proceedings of the International Symposium on Defect and
Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), Amsterdam,
October 2014.
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[58]
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Yuang Zhang, Li Li, Zhonghai Lu, Axel Jantsch, Minglun Gao, Hongbing Pan, and
Feng Han.
A survey of memory architecture for 3D chip
multi-processors.
Microprocessors and Microsystems, July 2014.
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DOI |
http ]
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[59]
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Yuang Zhang, Li Li, Zhonghai Lu, Axel Jantsch, Yuxiang Fu, and Minglun Gao.
Performance and network power evaluation of tightly mixed
SRAM NUCA for 3D Multi-core Network on Chips.
In IEEE International Symposium on Circuits and Systems
(ISCAS), pages 1961--1964, June 2014.
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[60]
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Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, and Axel Jantsch.
Designing 2D and 3D Network-on-Chip Architectures.
Springer, 2014.
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[61]
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Abbas Eslami Kiasari, Axel Jantsch, and Zhonghai Lu.
A Heuristic Framework for Designing and Exploring
Deterministic Routing Algorithm for NoCs.
In Maurizio Palesi and Masoud Daneshtalab, editors, Routing
Algorithms in Networks-on-Chip, chapter 2, pages 21--40. Springer, 2014.
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http ]
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[62]
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S. Liu, A. Jantsch, and Z. Lu.
A Fair and Maximal Allocator for Single-Cycle On-Chip
Homogeneous Resource Allocation.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions
on, October 2013.
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DOI |
.pdf ]
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[63]
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Abdul Naeem, Axel Jantsch, and Zhonghai Lu.
Scalability Analysis of Memory Consistency Models in NoC
based Distributed Shared Memory SoCs.
IEEE Transactions on Computer Aided Design of Integrated
Circuits and Systems, 32(5), May 2013.
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.pdf ]
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[64]
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Wenmin Hu, Zhonghai Lu, Hengzhu Liu, and Axel Jantsch.
Multicast Path Setup Incorporating Evicting.
Electronics and Electrical Engineering, 18(8), August 2012.
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.pdf ]
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[65]
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Martin Radetzki and Axel Jantsch.
Editorial introduction - Special issue on languages, models
and model based design for embedded systems.
Design Automation for Embedded Systems, July 2012.
Springer.
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.pdf ]
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[66]
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Jun Zhu, Ingo Sander, and Axel Jantsch.
Performance analysis of reconfigurations in adaptive
real-time streaming applications.
ACM Transactions in Embedded Computing Systems -- Special issue
on Embedded Systems for Real-time Multimedia, May 2012.
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.pdf ]
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[67]
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Xiaowen Chen, Zhonghai Lu, Axel Jantsch, and Shuming Chen.
Reducing Virtual-to-Physical address translation overhead in
Distributed Shared Memory based multi-core Network-on-Chips according to data
property.
Computers and Electrical Engineering, May 2012.
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.pdf ]
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[68]
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Huimin She, Zhonghai Lu, Axel Jantsch, and Li-Rong Zheng.
Estimation of Statistical Bandwidth through Backlog
Measurement.
In Workshop on Network Calculus (WoNeCa2012), March 2012.
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[69]
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Huimin She, Zhonghai Lu, Axel Jantsch, Dian Zhou, and Li-Rong Zheng.
Performance Analysis of Flow Based Traffic Splitting Strategy
on Cluster-Mesh Sensor Networks.
International Journal of Distributed Sensor Networks, 2012.
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.pdf ]
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[70]
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Huimin She, Zhonghai Lu, and Axel Jantsch.
System-Level Evaluation of Sensor Networks Deployment
Strategies: Coverage Lifetime and Cost.
In Proceedings of the 8th International Wireless Communications
and Mobile Computing Conference, 2012.
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[71]
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Ming Liu, Zhonghai Lu, Wolfgang Kuehn, and Axel Jantsch.
A Survey of FPGA Dynamic Reconfiguration Design Methodology
and Applications.
International Journal of Embedded and Real-Time Communication
Systems International Journal of Embedded and Real-Time Communication
Systems, 3(2):23--39, 2012.
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[72]
|
Wenmin Hu, Hengzhu Liu, Zhonghai Lu, Axel Jantsch, and Guitao Fu.
Self-selection pseudo-circuit: a clever crossbar
pre-allocation.
IEICE Electronics Express, 2012.
[ bib |
.pdf ]
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[73]
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Matt Grange, Axel Jantsch, Roshan Weerasekera, and Dinesh Pamunuwa.
Modeling the Computational Efficiency of 2-D and 3-D
Silicon Processors for Early-Chip Planning.
In Proceedings of the International Conference on CAD (ICCAD),
San Jose, CA, USA, November 2011.
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[74]
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Dinesh Pamunuwa, Matthew Grange, Roshan Weerasekera, and Axel Jantsch.
3-D Integration and the Limits of Silicon Computation.
In Proceedings of the International Conference on Very Large
Scale Integration (VLSI-SoC), Hong Kong, October 2011.
Invited Talk.
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[75]
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Ming Liu, Zhonghai Lu, Wolfgang Kuehn, and Axel Jantsch.
FPGA-based Particle Recognition in the HADES Experiment.
Design and Test of Computers, July-August 2011.
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.pdf ]
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[76]
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Huimin She, Zhonghai Lu, Axel Jantsch, Dian Zhou, and Li-Rong Zheng.
Modeling and Analysis of Rayleigh Fading Channels using
Stochastic Network Calculus.
In Proceedings of IEEE Wireless Communication and Networking
Conference (WCNC2011, Mexico, April 2011.
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[77]
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Ming Liu, Zhonghai Lu, Wolfgang Kuehn, and Axel Jantsch.
FPGA-based Cherenkov Ring Recognition in Nuclear and
Particle Physics Experiments.
In Proceedings of the 7th International Symposium on Applied
Reconfigurable Computing, belfast, UK, March 2011.
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[78]
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Ming Liu, Wolfgang Kuehn, Soeren Lange, Shua Yang, Johannes Roskoss, Zhonghai
Lu, Axel Jantsch, Qiang Wang, Hao Xu, Dapeng Jin, and Zhenan Liu.
A High-end Reconfigurable Computation Platform for Nuclear
and Particle Physics Experiments.
Computing in Science and Engineering, 13(2):52--63, March-April
2011.
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.pdf ]
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[79]
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Abbas Sheibanyrad, Frédéric Pétrot, and Axel Jantsch, editors.
3D Integartion for NoC-based SoC Architectures.
Integrated Circuits and Systems. Springer, January 2011.
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[80]
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Huimin She, Zhonghai Lu, Axel Jantsch, Dian Zhou, and Li-Rong Zheng.
Stochastic Coverage in Event-Driven Sensor Networks.
In Proceedings of the IEEE Symposium on Personal, Indoor, Mobile
and Radio Communications (PIMRC), Toronto, Canada, 9 2011.
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[81]
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Ming Liu, Zhonghai Lu, Wolfgang Kuehn, and Axel Jantsch.
Adaptively Reconfigurable Controller for the Flash Memory.
In Book of Flash Memory. InTech, 2011.
ISBN: 978-953-307-272-2.
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[82]
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Axel Jantsch, Matthew Grange, and Dinesh Pamunuwa.
The Promises and Limitations of 3-D Integration.
In Abbas Sheibanyrad, Frédéric Pétrot, and Axel Jantsch,
editors, 3D Integration for NoC-based SoC Architectures,
Integrated Circuits and Systems, chapter 2. Springer, 2011.
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[83]
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Ming Liu, Zhonghai Lu, Wolfgang Kuehn, and Axel Jantsch.
Inter-Process Communication using Pipes in FPGA-based
Adaptive Computing.
In Proceedings of the IEEE Annual Symposium on VLSI, Kefalonia,
Greece, July 2010.
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[84]
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Ming Liu, Zhonghai Lu, Wolfgang Kuehn, and Axel Jantsch.
Reducing FPGA Reconfiguration Time Overhead using Virtual
Configurations.
In Proceedings of the 5th International Workshop on
Reconfigurable Communication Centric Systems-on-Chip, Karlsruhe, Germany,
May 2010.
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[85]
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Jun Zhu, Ingo Sander, and Axel Jantsch.
Pareto Efficient Design for Reconfigurable Streaming
Applications on CPU/FPGAs.
In Proceedings of Design Automation and Test in Europe
(DATE '10), Dresden, Germany, March 2010.
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[86]
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Ming Liu, Zhonghai Lu, Wolfgang Kuehn, and Axel Jantsch.
FPGA-based Adaptive Computing for Correlated Multi-stream
Processing.
In Proceedings of the Conference Design, Automation and Test
Europe, Dresden, Germany, March 2010.
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[87]
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Jun Zhu, Ingo Sander, and Axel Jantsch.
Constrained Global Scheduling of Streaming Applications on
MPSoCs.
In Proceedings of the conference on Asia South Pacific
Design Automation (ASP-DAC '10), Taipei, Republic of China, January
2010.
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[88]
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Ming Liu, Zhonghai Lu, Wolfgang Kuehn, Shuo Yang, and Axel Jantsch.
A Reconfigurable Design Framework for FPGA Adaptive
Computing.
In Proceedings of the International Conference on ReConFigurable
Computing and FPGAs, Cancun, Mexico, December 2009.
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[89]
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Ming Liu, Wolfganga Kuehn, Zhonghai Lu, and Axel Jantsch.
Run-time Partial Reconfiguration Speed Investigation and
Architectural Design Space Exploration.
In Proceedings of the International Conference on Field
Programmable Logic and Applications, Prague, Chech Republic, September 2009.
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[90]
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Qiang Wang, Axel Jantsch, Dapeng Jin, Andreas Kopp, Wolfgang Kuehn, Johannes
Lang, Soeren Lange, Lu Li, Ming Liu, Zhen'an Liu, Zhonghai Lu, David
Muenchow, Johannes Roskoss, and Hao Xu.
Hardware/Software Co-design of an ATCA-based Computation
Platform for Data Acquisition and Triggering.
In 16th IEEE NPSS Real Time Conference, Beijing, May 2009.
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[91]
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Ming Liu, Axel Jantsch, Dapeng Jin, Andreas Kopp, Wolfgang Kuehn, Johannes
Lang, Lu Li, Soeren Lange, Zhen'an Liu, Zhonghai Lu, David Muenchow, Vladimir
Pechenov, Johannes Roskoss, Stephano Spataro, Qiang Wang, and Hao Xu.
Trigger Algorithm Development on FPGA-based Compute Nodes.
In 16th IEEE NPSS Real Time Conference, Beijing, May 2009.
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[92]
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Huimin She, Zhonghai Lu, Axel Jantsch, Dian Zhou, and Li-Rong Zheng.
Analytical Evaluation of Retransmission Schemes in Wireless
Sensor Networks.
In Proceedings of the IEEE 69th Vehicular Technology Conference:
VTC2009-Spring, April 2009.
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[93]
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Tiberiu Seceleanu and Axel Jantsch.
Modeling Communication with Synchronized Environments.
Fundamenta Informaticae, 86(3):343--369, October 2008.
[ bib |
.pdf ]
|
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[94]
|
Ming Liu, Tiago Perez, Johannes Lang, Shuo Yang, Wolfgang Kuehn, Hao Xu, Dapeng
Jin, Qiang Wang, Lu Li, Zhen'An Liu, Zhonghai Lu, and Axel Jantsch.
ATCA-based Computation Platform for Data Acquisition and
Triggering in Particle Physics Experiments.
In Proceedings of the International Conference on Field
Programmable Logic and Applications, September 2008.
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[95]
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Ming Liu, Wolfgang Kuehn, Zhonghai Lu, and Axel Jantsch.
System-on-an-FPGA Design for real-time Particle Track
recognition and Reconstruction in Physics Experiments.
In Proceedings of the Euromicro Diguital System Design
Conference, September 2008.
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Huimin She, Zhonghai Lu, and Axel Jantsch.
Deterministic Worst-case Performance Analysis for Wireless
Sensor Networks.
In Proceedings of the International Wireless Communications and
Mobile Computing Conference, Crete, Greece, August 2008.
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[97]
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Huimin She, Zhonghai Lu, Axel Jantsch, Li-Rong Zheng, and Dian Zhou.
Analysis of Traffic Splitting Mechanisms for 2D Mesh Sensor
Networks.
International Journal of Software Engineering and Its
Applications (IJSEIA), 2(3), July 2008.
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.pdf ]
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[98]
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Christoph Grimm, Axel Jantsch, Sandeep Shukla, and Eugenio Villar.
C-Based Design of Embedded Systems - Editorial.
EURASIP Journal on Embedded Systems, July 2008.
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[99]
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Iyad Al Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed
Bechara, Hasan Khalifeh, Axel Jantsch, and Rustam Nabiev.
A Multiprocessor System-on-Chip for Real-Time Biomedical
Monitoring and Analysis: ECG Prototype Architectural Design Space
Exploration.
ACM Transactions on Design Automation of Embedded Systems,
13(2), April 2008.
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|
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[100]
|
Tarvo Raudvere, Ingo Sander, and Axel Jantsch.
Application and Verification of Local Non-Semantic-Preserving
Transformations in System Design.
IEEE Transactions on Computer Aided Design of Integrated
Circuits and Systems, 27(6):1091--1103, 2008.
[ bib |
.pdf ]
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[101]
|
Huimin She, Zhonghai Lu, Axel Jantsch, Li-Rong Zheng, and Dian Zhou.
Traffic Splitting with Network Calculus for Mesh Sensor
Networks.
In Proceedings of the Future Generation Communication and
Networking (FGCN), December 2007.
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[102]
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Tomas Henriksson, Pieter van der Wolf, Axel Jantsch, and Alistair Bruce.
Network Calculus Applied to Verification of Memory Access
Performance in SoCs.
In Proceedings of the 5th IEEE Workshop on Embedded Systems for
Real-Time Multimedia, October 2007.
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[103]
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Tarvo Raudvere, Ingo Sander, and Axel Jantsch.
Synchronization after design refinements with sensitive delay
elements.
In Proceedings of the International Conference on HW/SW Codesign
and System Synthesis, Salzburg, Austria, September 2007.
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Andreas Herrholz, Frank Oppenheimer, P. A. Hartmann, Andreas Schallenberg,
Wolfgang Nebel, Christoph Grimm, Markus Damm, J. Haase, Fernando Herrera,
Eugenio Villar, Ingo Sander, Axel Jantsch, Anne-Marie Fouilliart, and Marcos
Martinez.
The ANDRES Project: ANalysis and Design of run-time
REconfigurable, heterogeneous Systems.
In Proceedings of the The International Conference on
Field-Programmable Logic, Reconfigurable Computing, and Applications (FPL),
August 2007.
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[105]
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Andreas Herrholz, Frank Oppenheimer, Andreas Schallenberg, Wolfgang Nebel,
Christoph Grimm, Markus Damm, Fernando Herrera, Eugenio Villar, Ingo Sander,
Axel Jantsch, Anne-Marie Fouilliart, and Marcos Martinez.
ANDRES - ANalysis and Design of run-time REconfigurable,
heterogeneous Systems.
In Workshop on Reconfigurable Systems at DATE, April 2007.
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Huimin She, Zhonghai Lu, Axel Jantsch, and Dian Zhou.
A Network-based System Architecture for Remote Medical
Applications.
In Proceedings of the Asia-Pacific Advanced Network Meeting,
2007.
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Tarvo Raudvere, Ingo Sander, and Axel Jantsch.
A Synchronization Algorithm for Local Temporal Refinements in
Perfectly Synchronous Models with Nested Feedback Loops.
In Proceedings of the Great Lake Symposium on VLSI (GLSVLSI),
2007.
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[108]
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Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsch, Shuo Yang, Tiago Perez,
and Zhenan Liu.
Hardware/Software Co-design of a General-Purpose Computation
Platform in Particle Physics.
In Proceedings of the ICFPT, 2007.
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[109]
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Iyad Al Khatib, Davide Bertozzi, Francesco Poletti, Luca Benini, Axel Jantsch,
Mohamed Bechara, Hasan Khalifeh, Mazen Hajjar, Rustam Nabiev, and Sven
Jonsson.
Hardware/Software Architecture for Real-Time ECG Monitoring
and Analysis Leveraging MPSoC Technology.
Transactions on High-Performance Embedded Architectures and
Compilers (HiPEAC), I(1):239--258, 2007.
LNCS 4050.
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.pdf ]
|
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[110]
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T. Seceleanu, A. Jantsch, and H. Tenhunen.
On-Chip Distributed Architectures.
In Proceedings of the IEEE International SOC Conference, pages
329 -- 330, September 2006.
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Weixing Wang and Axel Jantsch.
A New Protocol for Electing Cluster head Based on Maximum
Residual Energy.
In Proceedings of the IEEE International Cross-Layer Designs and
Protocols Symposium, July 2006.
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[112]
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Iyad Al-Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed
Bechara, Hasan Khalifeh, Axel Jantsch, and Rustam Nabiev.
A Multiprocessor System-on-Chip for Real-Time Biomedical
Monitoring and Analysis: Architectural Design Space Exploration.
In Proceedings of the Design Automation Conference, July 2006.
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[113]
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Tiberiu Seceleanu and Axel Jantsch.
Communicating with Synchronized Environments.
In Proceedings of the Sixth International Conference on
Application of Concurrency to System Design, June 2006.
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Axel Jantsch.
Nocsim: A NoC Simulator.
School of Information and Communication Technology, Royal Institute
of Technology, Stockholm, version 0.4 alpha edition, 2006.
[ bib ]
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[115]
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Weixing Wang, Axel Jantsch, and Shuran Song.
An algorithm of electing cluster head in beacon node
distributions based on maximum residual energy.
In Proceedings of Annual Conference on Chinese Society of
Agricultural Engineering, volume 3:535-539, Guangzhou City, P. R. of China,
December 2005.
[ bib |
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[116]
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Abhijit K. Deb, Axel Jantsch, and Johnny Öberg.
System Design for DSP Applications in Transaction Level
Modeling Paradigm.
In Proc. Design Automation Conf. (DAC), pages 466--471, San
Diego, California, June 2004.
[ bib |
.pdf ]
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[117]
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Jari Nurmi, Hannu Tenhunen, Jouni Isoaho, and Axel Jantsch, editors.
Interconnect-Centri Design for Advanced SoCs and NoCs.
Kluwer Academic Publisher, April 2004.
[ bib ]
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[118]
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Ingo Sander, Axel Jantsch, and Hannu Tenhunen.
The Platform as Interface in a SoC Design Curriculum.
In Proceedings of te 5t European Worksop on Microelectronics
Education, April 2004.
[ bib ]
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[119]
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Tarvo Raudvere, Ashish Kumar Singh, Ingo Sander, and Axel Jantsch.
Polynomial Abstraction for Verification of Sequentially
Implemented Combinational Circuits.
In Proceedings of the Design Automation and Test Europe
Conference (DATE), February 2004.
interactive presentation.
[ bib ]
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[120]
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Axel Jantsch, Johnny Öberg, and Hannu Tenhunen.
Introduction to Special Issue on Networks on Chip.
Journal of Systems Architecture, 50(2-3), February 2004.
[ bib ]
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[121]
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Abhijit K. Deb, Axel Jantsch, and Johnny Öberg.
System Design for DSP Applications Using the MASIC
Methodology.
In Proceedings of the Design Automation and Test Europe (DATE),
February 2004.
[ bib ]
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[122]
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Martti Forsell, Juha-Pekka Soininen, Kari Tiensyriä, Axel Jantsch, Klaus
Kronlöf, and Bojidar Hadjiski.
Networks on Chip: Approaches and Challenges.
In Research and Development Activities in Telecommunication
Systems. VTT Electronics, 2004.
[ bib |
http ]
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[123]
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Yutai Ma, Axel Jantsch, and Hannu Tenhunen.
A Group of Subword Instructions and Design Issues for Network
Processing RISC Cores.
In Proceedings of the IEEE NorChip Conference, November 2003.
[ bib ]
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[124]
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Abhijit K. Deb, Johnny Öberg, and Axel Jantsch.
Simulation and Analysis of Embedded DSP Systems using
Petri Nets.
In Proceedings of the 14th IEEE International Workshop on Rapid
System Prototyping, June 2003.
[ bib ]
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[125]
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Abhijit K. Deb, Johnny Öberg, and Axel Jantsch.
Simulation and Analysis of Embedded DSP Systems using
MASIC Methodology.
In Proceedings of the Design Automation and Test Europe (DATE),
March 2003.
[ bib ]
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[126]
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Juha-Pekka Soininen, Axel Jantsch, Martti Forsell, Antti Pelkonen, Jari Kreku,
and Shashi Kumar.
Extending Platform-Based Design to Network on Chip Systems.
In Proceedings of the International Conference on VLSI Design,
January 2003.
[ bib |
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[127]
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Yutai Ma, Axel Jantsch, and Hannu Tenhunen.
Two special register addressing modes for internet protocol
processing.
In Proc. of International Network Conference, Plymouth, United
kingdom, July 2002.
[ bib ]
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[128]
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Ingo Sander and Axel Jantsch.
Transformation Based Communication and Clock Domain
Refinement for System Design.
In Proceedings of Design Automation Conference, June 2002.
[ bib |
.pdf ]
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[129]
|
Tero Nurmi, Hannu Tenhunen, Li-Rong Zheng, Axel Jantsch, Jari Nurmi, and Jouni
Isoaho.
Physical Performance Modelling for Platform-based SoC
Design.
In Proceedings of the 4th European Workshop on Microelectronics
Education, May 2002.
[ bib ]
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[130]
|
Per Bjureus, Mickael Millberg, and Axel Jantsch.
FPGA Resource and Timing Estimation from Matlab Execution
Traces.
In Proceedings of the International Workshop on
Hardware/Software Codesign, May 2002.
[ bib ]
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[131]
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Yutai Ma, Axel Jantsch, and Hannu Tenhunen.
Load/Store Unit Design of a Programmable Internet Protocol
Processor.
In Proceedings of Swedish System-on-Chip Conference, March
2002.
[ bib ]
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[132]
|
Abhijit Kumar Deb, Johnny Oberg, and Axel Jantsch.
Performance Analsysi and Architectural Refinement of Embedded
DSP Systems in the MASIC Methodology.
In Proceedings of Swedish System-on-Chip Conference, March
2002.
[ bib ]
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[133]
|
Abhijit K. Deb, Johnny Öberg, and Axel Jantsch.
Control and Communication Performance Analysis of Embedded
DSP Systems in the MASIC Methodology.
In Proceedings of the International Symposium on System
Synthesis (ISSS), October 2001.
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[134]
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Per Bjuréus and Axel Jantsch.
Performance Analysis with Confidence Intervals for Embedded
Software Processes.
In Proceedings of the International Symposium on System
Synthesis (ISSS), October 2001.
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[135]
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Per Bjuréus and Axel Jantsch.
Modeling of Mixed Control and Dataflow Systems in MASCOT.
IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, 9(5):690--704, October 2001.
[ bib ]
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[136]
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Mattias O'Nils and Axel Jantsch.
Device Driver and DMA Controller Synthesis from HW/SW
Communication Protocol Specifications.
Design Automation of Embedded Systems, 6(2):177 -- 207, April
2001.
[ bib |
.pdf ]
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[137]
|
Johnny Öberg, Mattias O'Nils, Axel Jantsch, Adam Postula, and Ahmed Hemani.
Grammar-based Design.
Journal of Systems Architecture, 47(3-4):225--240, April 2001.
[ bib ]
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[138]
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Yutai Ma, Axel Jantsch, and Hannu Tenhunen.
A Flexible Register Access Control for Programmable Protocol
Processors.
In Proceedings of the 44th Midwest Symposium on Circuits and
Systems (MWSCAS), August 2001.
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[139]
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A. Jantsch, S. Kumar, I. Sander, B. Svantesson, J. Öberg, A. Hemani, Peeter
Ellervee, and Mattias O'Nils.
A Comparison of Six Languages for System Level Description of
Telecom Applications.
In Jean Mermet, editor, Electronic Chips & System Design
Languages, chapter 15, pages 181--192. Kluwer Academic Publisher, 2001.
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[140]
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Per Bjuréus and Axel Jantsch.
Heterogenous System-level Cosimulation with SDL and
Matlab.
In Jean Mermet, editor, Electronic Chips & System Design
Languages, chapter 12, pages 145--157. Kluwer Academic Publisher, 2001.
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[141]
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Yutai Ma, Axel Jantsch, and Hannu Tenhunen.
A Programmable Protocol Processor Architecture for High Speed
Internet Protocol Processing.
In Proceedings of the IEEE NORCHIP Conference, November 2000.
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[142]
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Wenbiao Wu, Ingo Sander, and Axel Jantsch.
Transformational System Design based on a Formal
Computational Model and Skeletons.
In Proceedings of the Forum on Design Languages, September
2000.
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[143]
|
Johan Ditmar, Kjell Torkelsson, and Axel Jantsch.
A Dynamically Reconfigurable FPGA-based Content Addressable
Memory for Internet Protocol Characterization.
In Reiner W. Hartenstein and Herbert Grunbacher, editors,
Proceedings of the 10th International Conference on Field Programmable Logic
and Applications, volume 1896 of Lecture Notes in Computer Science,
pages 19--28. Springer Verlag, August 2000.
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[144]
|
Axel Jantsch, Shashi Kumar, and Ahmed Hemani.
A Metamodel for Studying Concepts in Electronic System
Design.
IEEE Design & Test of Computers, 17(3):78--85, July-September
2000.
[ bib |
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|
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[145]
|
Axel Jantsch, Johann Notbauer, and Thomas Albrecht.
Functional Validation for Large Telecom Systems.
Design Automation of Embedded Systems, Kluwer, 5(1), February
2000.
[ bib |
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|
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[146]
|
Patrick Schaumont, Mary Sheeran, Satnam Singh, and Axel Jantsch.
Object Oriented Approach versus Functional Approach in System
Design.
In Proceedings of the Forum on Design Languages, 2000.
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[147]
|
Yutai Ma, Axel Jantsch, and Hannu Tenhunen.
A Simple Transition Control for FSM Programmable Protocol
Processors.
In Proceedings of the 43rd Midwest Symposium on Circuits and
Systems (MWSCAS), August 2000.
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[148]
|
Axel Jantsch and Per Bjuréus.
Composite Signal Flow: A Computational Model Combining
Events, Sampled Streams, and Vectors.
In Proceedings of the Design and Test Europe Conference (DATE),
2000.
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[149]
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Per Bjuréus and Axel Jantsch.
MASCOT: A Specification and Cosimulation Method Integrating
Data and Control Flow.
In Proceedings of the Design and Test Europe Conference (DATE),
2000.
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[150]
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Ingo Sander and Axel Jantsch.
System Synthesis Utilizing a Layered Functional Model.
In Proceedings of the 7th International Workshop on
Hardware/Software Codesign, pages 136--141, May 1999.
[ bib ]
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[151]
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Ingo Sander and Axel Jantsch.
System Synthesis Based on a Formal Computational Model and
Skeletons.
In Proceedings of the IEEE Computer Society Annual Workshop on
VLSI, 1999.
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[152]
|
Ingo Sander and Axel Jantsch.
Formal Design Based on the Synchronous Approach, Functional
Models and Skeletons.
In Proceedings of the Twelfth International Conference on VLSI
Design, 1999.
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[153]
|
Henrik Olson, Axel Jantsch, and Hannu Tenhunen.
Floating- to Fixed-Point Refinement in Matlab with an
Object-Oriented Library.
In Proceedings of the IEEE Norchip Conference, 1999.
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[154]
|
Mattias O'Nils and Axel Jantsch.
Operating System Sensitive Device Driver Synthesis from
Implementation Independent Protocol Specification.
In Proceedings of Design Automation and Test in Europe, 1999.
[ bib ]
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[155]
|
Mattias O'Nils and Axel Jantsch.
Synthesis of DMA Controllers from Architecture Independent
Descriptions of HW/SW Communication Protocols.
In Proceedings of the Twelfth International Conference on VLSI
Design, January 1999.
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[156]
|
Thomas Meincke, Axel Jantsch, Peeter Ellervee, Ahmed Hemani, and Hannu
Tenhunen.
A Generic Scheme for Communication Representation and
Mapping.
In Proceedings of to IEEE Norchip Conference, 1999.
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[157]
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Axel Jantsch, Shashi Kumar, and Ahmed Hemani.
The Rugby Model: A Framework for the Study of Modelling,
Analysis, and Synthesis Concepts in Electronic Systems.
In Proceedings of Design Automation and Test in Europe (DATE),
1999.
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[158]
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Axel Jantsch.
Integrated Electronic Systems Program - A National Research
Program.
In EDA-Traff'99, 1999.
[ bib ]
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[159]
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Axel Jantsch.
Formal System Specification Models for Verification and
Refinement.
In EDA-Traff'99, 1999.
[ bib ]
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[160]
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Wolfgang Horn, Bengt Svantesson, Shashi Kumar, Axel Jantsch, and Ahmed Hemani.
Hardware Synthesis of an ATM Multiplexer Modelled in SDL: A
Case Study.
In Proceedings of the IEEE Computer Society Annual Workshop on
VLSI, 1999.
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[161]
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Per Bjuréus and Axel Jantsch.
Heterogenous System-level Cosimulation with SDL and
Matlab.
In Proceedings of the Forum on Design Languages (FDL), 1999.
[ bib ]
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[162]
|
Mattias O'Nils and Axel Jantsch.
HW/SW Interface Validation in IP based System Design.
In Proceedings of the International Workshop on IP Based
Synthesis and System Design, December 1998.
[ bib ]
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[163]
|
Mattias O'Nils and Axel Jantsch.
Refinement of HW/SW Communication Channels: Case Study
and Comparison.
In Proceedings of the 16th NORCHIP Conference, November 1998.
[ bib ]
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[164]
|
Mattias O'Nils and Axel Jantsch.
Multi-phase Validation of Hardware/Software Interfaces based
on Generated Simulation Models.
In Proceedings of the IEEE International High Level Design
Validation and Test Workshop, November 1998.
[ bib ]
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[165]
|
Johnny Oeberg, Axel Jantsch, and Ahmed Hemani.
Validation of Interface Protocols Using Grammar-based
Models.
In Proceedings of the IEEE International High Level Design
Validation and Test Workshop, 1998.
[ bib ]
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[166]
|
Mattias O'Nils, Johnny Öberg, and Axel Jantsch.
Grammar Based Modelling and Synthesis of Device Drivers and
Bus Interfaces.
In Proceedings of the 24th Euromicro Conference, short
contribution, Vasteras, 1998.
[ bib ]
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[167]
|
A. Jantsch, S. Kumar, I. Sander, B. Svantesson, J. Öberg, and A. Hemani.
Comparison of Six Languages for System Level Descriptions of
Telecom Systems.
In Proceedings of the Forum on Design Languages, volume 2,
1998.
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[168]
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Axel Jantsch, Johnny Öberg, and Ahmed Hemani.
Is there a Niche for a General Protocol Processor ?
In Proceeedings of 16th NORCHIP Conference, 1998.
[ bib ]
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[169]
|
Peeter Ellervee, Shashi Kumar, Axel Jantsch, Bengt Svantesson, Thomas Meincke,
and Ahmed Hemani.
IRSYD: An Internal Representation for Heterogeneous
Embedded Systems.
In Proceedings of the 16th NORCHIP Conference, 1998.
[ bib ]
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[170]
|
Johnny Öberg, Anshul Kumar, and Axel Jantsch.
An Object-Oriented Concept for Intelligent Library
Functions.
In Proceedings of the Eleventh International Conference on VLSI
Design, January 1998.
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[171]
|
Mattias O'Nils and Axel Jantsch.
Communication in Hardware/Software Embedded Systems - A
Taxonomy and Problem Formulation.
In Proceedings of the 15th NORCHIP Conference, November 1997.
[ bib ]
|
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[172]
|
Axel Jantsch, Johann Notbauer, and Thomas Albrecht.
Testcase Development for Large Telecom Systems.
In Proceedings of the International High-level Design Validation
and test Workshop, November 1997.
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|
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[173]
|
Shashi Kumar, Axel Jantsch, Peeter Ellervee, Ahmed Hemani, and Anshul Kumar.
Internal Representation for Specification and Design of
Heterogenous Systems.
In Third Workshop on Systems Design Languages, Italy, July
1997.
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[174]
|
Axel Jantsch.
Limitations of Interactive Design.
In Workshop on Electronic Design Processes, 1997.
http://www.cse.nd.edu/ cseda/edpw97/.
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[175]
|
L. Hellberg, A. Hemani, J. Isoaho, A. Jantsch, M. Mokhtari, and H. Tenhunen.
Integration of Physical and Functional Electronic System
Representations in Electronic Curriculum.
In Proceedings of the 15th NORCHIP Conference, 1997.
[ bib ]
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[176]
|
L. Hellberg, A. Hemani, J. Isoaho, A. Jantsch, M. Mokhtari, and H. Tenhunen.
System Oriented VLSI Curriculum at KTH.
In Proceedings of the International Conference on
Microelectronic Systems Educations, MSE97, 1997.
[ bib ]
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[177]
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Kalle Tammemae, Mattias O'Nils, Axel Jantsch, and Ahmed Hemani.
Hardware/Software Cosynthesis for Reconfigurable Systems.
In Proceedings of IEE Colloquium Hardware-Software Cosynthesis
for Reconfigurable Systems, February 1996.
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[178]
|
Johnny Öberg, Jouni Isoaho, Peeter Ellervee, Axel Jantsch, and Ahmed Hemani.
A Rule-based Approach for Improving Allocation of Filter
Structures in HLS.
In Proceedings of VLSI Design 96, 1996.
[ bib ]
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[179]
|
A. Hemani, B. Svantesson, P. Ellervee, A.Postula, J. Öberg, A.Jantsch, and
H. Tenhunen.
High-level Synthesis of Control and Memory Intensive
Communication Systems.
In Proceedings of the 1995 ASIC Conference and Exhibit, Austin,
Texas, September 1995.
[ bib ]
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[180]
|
Mattias O'Nils, Axel Jantsch, Ahmed Hemani, and Hannu Tenhunen.
Interactive Hardware-Software Partitioning and Memory
Allocation Based on Data Transfer Profiling.
In International Conference on Recent Advances in Mechatronics,
August 1995.
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[181]
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T. Lazraq, B. Svantesson, A. Jantsch, and A. Hemani.
Modelling of Operation and Maintance Functions in the ATM
Network.
In Proc. of the 9th European Simulation Multiconference, June
1995.
[ bib ]
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[182]
|
Ahmed Hemani, Bengt Svantesson, Peeter Ellervee, Adam Postula, Axel Jantsch,
and Hannu Tenhunen.
Trade-offs in High-level Synthesis of Telecommunication
Circuits.
In Proceedings of SASIMI'95, Japan, 1995.
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[183]
|
Johnny Öberg, Peeter Ellervee, Mehran Mokhtari, Axel Jantsch, and Ahmed
Hemani.
A 1 GIPS Peak Performance Multi-Threaded Processor Core Using
Interleaved Processing And A Revolving register File Targeted for GaAs.
In 5th Swedish Workshop on Computer System Architecture
(DSA'95), 1995.
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[184]
|
J. Öberg, J. Isoaho, P. Ellervee, A. Jantsch, and A. Hemani.
BABBAGE - A Rule based Tool for Synthesis of Hardware
Systems.
In Proceedings of the IEEE NORCHIP Conference, November 1994.
[ bib ]
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[185]
|
J. Öberg, P. Ellervee, M. Mokhtari, and A. Jantsch.
Design of a 1 GIPS Peak Performance Processor using GaAs
Technology.
In Proceedings of the IEEE NORCHIP Conference, November 1994.
[ bib ]
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[186]
|
Peeter Ellervee, Johnny Öberg, Axel Jantsch, and Ahmed Hemani.
Neural Network Based Estimator to Explore the Design Space at
System Level.
In Procceedings of the Biennial Baltic Electronic Conference,
Tallin, October 1994.
[ bib ]
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[187]
|
Jouni Isoaho and Axel Jantsch.
DSP Development with Full-Speed Prototyping Based on
HW-SW Codesign Techniques.
In Proc. of the Fourth International Workshop on Field
programmable Logic and Applications, Prague, FPL'94, September 1994.
[ bib ]
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[188]
|
Axel Jantsch and Jouni Isoaho.
A Versatile Design Validation Environment by Means of
Software Execution, Hardware Simulation, and Emulation.
In Proc. of the 36th SIMS Simulation Conference, pages 322 --
325. Scandinavian Simulation Society, August 1994.
[ bib ]
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[189]
|
Axel Jantsch, Jouni Isoaho, and Johnny Öberg.
Hardware-Software Codesign for Multirate DSP System
Development.
In Poster session of Third International Workshop on
Hardware-Software Codesign, Grenoble, September 1994.
[ bib ]
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[190]
|
Axel Jantsch, Peeter Ellervee, Johnny Öberg, Ahmed Hemani, and Hannu
Tenhunen.
Hardware-Software Partitioning and Minimizing Memory
Interface Traffic.
In Proceedings of EURO-DAC '94, Grenoble, France, September
1994.
[ bib |
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|
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[191]
|
Axel Jantsch, Peeter Ellervee, Johnny Öberg, Ahmed Hemani, and Hannu
Tenhunen.
A Software Oriented Approach to Hardware/Software Codesign.
In Proceedings of the Poster Session of CC'94, International
Conference on Compiler Construction, Edinburgh, April 1994.
[ bib ]
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[192]
|
Axel Jantsch, Peeter Ellervee, Johnny Öberg, and Ahmed Hemani.
A Case Study on Hardware/Software Partitioning.
In Proceedings of IEEE Workshop on FPGAs for Custom Computing
Machines, Napa, CA, April 1994.
[ bib ]
|
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[193]
|
Peeter Ellervee, Axel Jantsch, Johnny Öberg, Ahmed Hemani, and Hannu
Tenhunen.
Exploring ASIC Design Space at System Level with a Neural
Network Estimator.
In 7th Annual IEEE International ASIC Conference, ASIC'94,
1994.
[ bib ]
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[194]
|
Axel Jantsch.
Hades: An Environment for Design Space Exploration.
In Proceedings of GME Fachtagung Mikroelektronik, March 1993.
[ bib ]
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[195]
|
Axel Jantsch.
Design Space Exploration with Design Style Description and
Estimation Functions.
PhD thesis, Vienna University of Technology, Institut für
Technische Informatik, September 1992.
[ bib ]
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[196]
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Axel Jantsch.
A Capability Library for High Level Synthesis.
In Workshop on Control Dominated Synthesis, 1992.
[ bib ]
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[197]
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Axel Jantsch.
Probleme der Morphologie bei sprachanalysierenden Systemen.
Master's thesis, Vienna University of Technology, 1988.
[ bib ]
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[198]
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Amir Rahmani, Axel Jantsch, and Nikil Dutt.
SAGE-CPSoC: Self-Aware CPSoCs with Hierarchical Goal
Management.
Marie-Slodovska-Curie Action with Global Fellow Amir Rahmani,
Cooperation between TU Wien and UC Irvine, Project number 705617., 2016-2019.
[ bib ]
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