[1]	Nikil Dutt, Axel Jantsch, and Santanu Sarma. Self-aware cyber-physical systems-on-chip. In Proceedings of the International Conference for Computer Aided Design, Austin, Texas, USA, November 2015. invited. [ bib | .pdf ]
[2]	Awet Yemane Weldezion, Matt Grange, Axel Jantsch, Hannu Tenhunen, and Dinesh Pamunuwa. Zero-load predictive model for performance analysis in deflection routing NoCs. Journal of Microprocessors and Microsystems, 39(8), November 2015. [ bib | DOI ]
[3]	Anil Kanduri, Mohammad-Hashem Haghbayan, Amir-Mohammad Rahmani, Pasi Liljeberg, Axel Jantsch, and Hannu Tenhunen. Dark silicon aware runtime mapping for many-core systems: A patterning approach. In Proceedings of the International Conference on Computer Design (ICCD), pages 610--617, New York City, USA, October 2015. [ bib | .pdf ]
[4]	Nima TaheriNejad, Sai Manoj P. D., and Axel Jantsch. Memristors' potential for multi-bit storage and pattern learning. In Proceedings of the 9th European Modelling Symposium on Mathematical Modelling and Computer Simulation, Madrid, Spain, October 2015. [ bib | .pdf ]
[5]	Mohammad-Hashem Haghbayan, Anil Kanduri, Amir-Mohammad Rahmani, Pasi Liljeberg, Axel Jantsch, and Hannu Tenhunen. MapPro: Proactive runtime mapping for dynamic workloads by quantifying ripple effect of applications on networks-on-chip. In Proceedings of the International Symposium on Networks on Chip, Vancouver, Canada, September 2015. [ bib | .pdf ]
[6]	Shaoteng Liu, Zhonghai Lu, and Axel Jantsch. Highway in TDM NoCs. In Proceedings of the International Symposium on Networks on Chip, Vancouver, Canada, September 2015. Best Paper Award. [ bib | .pdf ]
[7]	Andreas Steininger, Horst Zimmermann, Axel Jantsch, Michael Hofbauer, Ulrich Schmid, Kurt Schweiger, and Varadan Savulimedu Veeravalli. Building reliable systems-on-chip in nanoscale technologies. Elektrotechnik & Informationstechnik, 132(6):301--306, August 2015. [ bib | DOI | .pdf ]
[8]	Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Yang Li, Shuming Chen, Yang Guo, Zonglin Liu, Jianghua Wan, Jianzhuang Lu, Shuwei Sun, Shenggang Chen, Hu Chen, and Man Liao. Achieving memory access equalization via round-trip routing latency prediction in 3D many-core. In IEEE Annual Symposium on VLSI (ISVLSI), Montpelllier, France, July 2015. [ bib | .pdf ]
[9]	J.-S. Preden, K. Tammemäe, A. Jantsch, M. Leier, A. Riid, and E. Calis. The benefits of self-awareness and attention in fog and mist computing. IEEE Computer, Special Issue on Self-Aware/Expressive Computing Systems, pages 37--45, July 2015. [ bib | DOI ]
[10]	Amirmohammad Rahmani, Hannu Tenhunen, Pasi Liljeberg, Awet Yemane Weldezion, Srinivasa Kanduru, Juha Plosila, Mohammadhashem Haghbayan, and Axel Jantsch. Dynamic power management for many-core platforms in the dark silicon era: A multi-objective control approach. In Proceedings of the International Symposium on Low Power Electronics and Design, Rome, Italy, July 2015. [ bib | .pdf ]
[11]	Junshi Wang, Masoumeh Ebrahimi, Letian Huang, Axel Jantsch, and Guangjun Li. Design of fault-tolerant and reliable networks-on-chip. In IEEE Annual Symposium on VLSI (ISVLSI), Montpelllier, France, July 2015. [ bib | .pdf ]
[12]	Fahimeh Jafari, Zhonghai Lu, and Axel Jantsch. Least upper delay bound for VBR flows in networks-on-chip with virtual channels. ACM Trans. Design Autom. Electr. Syst., 20(3):35:1--35:33, June 2015. [ bib | DOI | http ]
[13]	Runan Ma, Zhida Hui, and Axel Jantsch. A packet-switched interconnect for many-core systems with BE and RT service. In Proceedings of the Design Automation and Test Europe Conference (DATE), Grenoble, France, March 2015. [ bib | DOI ]
[14]	Xiaofan Zhang, Masoumeh Ebrahimi, Letian Huang, Guangjun Li, and Axel Jantsch. A network-level solution for fault detection, masking, and tolerance in NoCs. In Proceedings of 23rd IEEE Euromicro Conference on Parallel, Distributed and Network-Based Computing, (PDP), Finland, March 2015. [ bib | .pdf ]
[15]	Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Yang Guo, Shenggang Chen, and Hu Chen. Performance analysis of homogeneous on-chip large-scale parallel computing architectures for data-parallel applications. Journal of Electrical and Computer Engineering, 2015. [ bib | DOI | .pdf ]
[16]	Shaoteng Liu, Axel Jantsch, and Zhonghai Lu. MultiCS: Circuit switched NoC with multiple sub-networks and sub-channels. Journal of Systems Architecture, 2015. [ bib | DOI | .pdf ]
[17]	Yuang Zhang, Li Li, Axel Jantsch, Zhonghai Lu, Minglun Gao, Yuxiang Fu, and Hongbing Pan. Exploring stacked main memory architecture for 3D GPGPUs. In IEEE International Conference on ASIC (ASICON), Chengdu, China, 2015. [ bib | .pdf ]