[1]	Xiaowen Chen, Zhonghai Lu, Shuming Chen, and Axel Jantsch. Run-time partitioning of hybrid distributed shared memory on multi-core network-on-chips. In The 3rd IEEE International Symposium on Parallel Architectures, Algorithms and Programming (PAAP 2010), Dalian, China, December 2010. [ bib | .pdf ]
[2]	Fahimeh Jafari, Zhonghai Lu, Axel Jantsch, and Mohammad Hossein Yaghmaee. Buffer optimization in network-on-chip through flow regulation. IEEE Transactions on Computer Aided Design (TCAD), 29(12):1973--1986, December 2010. [ bib | http ]
[3]	Xiaowen Chen, Shuming Chen, Zhonghai Lu, and Axel Jantsch. Area and performance optimization of barrier synchronization on multi-core network-on-chips. In 3rd IEEE International Conference on Computer and Electrical Engineering (ICCEE), Chengdu, China, November 2010. [ bib | .pdf ]
[4]	Xiaowen Chen, Shuming Chen, Zhonghai Lu, and Axel Jantsch. Multi-FPGA implementation of a network-on-chip based many-core architecture with fast barrier synchronization mechanism. In Proceedings of the IEEE Norchip Conference, Tampere, Finland, November 2010. [ bib | .pdf ]
[5]	Chaochao Feng, Zhonghai Lu, Axel Jantsch, Jinwen Li, and Minxuan Zhang. A reconfigurable fault-tolerant deflection routing algorithm based on reinforcement learning for networks-on-chip. In Proceedings of the International Workshop on Network on Chip Architectures (NoCArc), Atlanta, Gorgia, November 2010. [ bib | .pdf ]
[6]	Abbas Eslami Kiasari, Axel Jantsch, and Zhonghai Lu. A framework for designing congestion-aware deterministic routing. In Proceedings of the International Workshop on Network on Chip Architectures (NoCArc), Atlanta, Gorgia, November 2010. [ bib | .pdf ]
[7]	Xiaowen Chen, Zhonghai Lu, Axel Jantsch, and Shuming Chen. Handling shared variable synchronization in multi-core network-on-chip with distributed memory. In International SOC Conference, Las Vegas, Nevada, September 2010. [ bib | .pdf ]
[8]	Zhipeng Chen and Axel Jantsch. A worst case performance model for TDM virtual circuit in nocs. In Proceedings of the International Workshop on Network on Chip, Zheng Zhou, China, September 2010. [ bib | .pdf ]
[9]	Chaochao Feng, Zhonghai Lu, Axel Jantsch, Jinwen Li, and Minxuan Zhang. FoN: Fault-on-neighbor aware routing algorithm for networks-on-chip. In International SOC Conference, Las Vegas, Nevada, September 2010. [ bib | .pdf ]
[10]	Jun Zhu, Ingo Sander, and Axel Jantsch. HetMoC: Heterogeneous modeling in systemc. In Proceedings of the Forum on Design Langauges (FDL), Southhampton, UK, September 2010. [ bib | .pdf ]
[11]	Bernard Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Dimitris Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, Ahmed Hemani, Axel Jantsch, Geert Vanmeerbeeck, Jari Kreku, Kari Tiensyrja, Fragkiskos Ieromnimon, Dimitrios Kritharidis, Andreas Wiefrink, Bart Vanthournout, and Philippe Martin. Mapping optimisation for scalable multi-core architecture: The MOSART approach. In Proceedings of the IEEE Annual Symposium on VLSI, Kefalonia, Greece, July 2010. [ bib | .pdf ]
[12]	Xiaowen Chen, Zhonghai Lu, Axel Jantsch, and Shuming Chen. Supporting efficient synchronization in multi-core NoCs using dynamic buffer allocation technique. In Proceedings of the IEEE Annual Symposium on VLSI, Kefalonia, Greece, July 2010. [ bib | .pdf ]
[13]	Ming Liu, Zhonghai Lu, Wolfgang Kuehn, and Axel Jantsch. Inter-process communication using pipes in FPGA-based adaptive computing. In Proceedings of the IEEE Annual Symposium on VLSI, Kefalonia, Greece, July 2010. [ bib | .pdf ]
[14]	Abdul Naeem, Xiaowen Chen, Zhonghai Lu, and Axel Jantsch. Scalability of weak consistency in NoC based multicore architectures. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France, June 2010. [ bib | .pdf ]
[15]	Ming Liu, Zhonghai Lu, Wolfgang Kuehn, and Axel Jantsch. Reducing FPGA reconfiguration time overhead using virtual configurations. In Proceedings of the 5th International Workshop on Reconfigurable Communication Centric Systems-on-Chip, Karlsruhe, Germany, May 2010. [ bib | .pdf ]
[16]	Amr Helmy, Laurence Pierre, and Axel Jantsch. Theorem proving techniques for formal verification of noc communications with non-minimal adaptive routing. In Proceedings of the 13th IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems, Vienna, Austria, April 2010. [ bib | .pdf ]
[17]	Xiaowen Chen, Zhonghai Lu, Axel Jantsch, and Shuming Chen. Supporting distributed shared memory on multi-core network-on-chips using a dual microcoded controller. In Proceedings of the confernece for Design Automation and Test in Europe, Dresden, Germany, March 2010. [ bib | .pdf ]
[18]	Fahimeh Jafari, Zhonghai Lu, Axel Jantsch, and Mohammad H. Yaghmaee. Optimal regulation of traffic flows in networks-on-chip. In Proceedings of the Design Automation and Test Europe Conference (DATE), Dresden, March 2010. [ bib | .pdf ]
[19]	Ming Liu, Zhonghai Lu, Wolfgang Kuehn, and Axel Jantsch. FPGA-based adaptive computing for correlated multi-stream processing. In Proceedings of the Conference Design, Automation and Test Europe, Dresden, Germany, March 2010. [ bib | .pdf ]
[20]	Jun Zhu, Ingo Sander, and Axel Jantsch. Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs. In Proceedings of Design Automation and Test in Europe (DATE '10), Dresden, Germany, March 2010. [ bib | .pdf ]
[21]	Jun Zhu, Ingo Sander, and Axel Jantsch. Constrained global scheduling of streaming applications on MPSoCs. In Proceedings of the conference on Asia South Pacific Design Automation (ASP-DAC '10), Taipei, Republic of China, January 2010. [ bib | .pdf ]