[1]
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Ahsen Ejaz and Axel Jantsch.
Costs and benefits of flexibility in spatial division circuit
switched networks-on-chip.
In Proceedings of the Sixth International Workshop on Network on
Chip Architecture, Davis, CA, December 2013.
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[2]
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S. Liu, A. Jantsch, and Z. Lu.
A fair and maximal allocator for single-cycle on-chip homogeneous
resource allocation.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions
on, October 2013.
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DOI |
.pdf ]
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[3]
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Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa, Axel Jantsch, and Hannu
Tenhunen.
A scalable multi-dimensional NoC simulation model for diverse
spatio-temporal traffic pattern.
In Proceedings of the 3D Systems Integration Conference
(3DIC), San Francisco, California, USA, October 2013.
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.pdf ]
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[4]
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Jiajie Zhang, Zheng Yu, Zhiyi Yu, Kexin Zhang, Zhonghai Lu, and Axel Jantsch.
Efficient distributed memory management in a multi-core H.264
decoder on FPGA.
In Proceedings of the International Symposium on System on
Chip, Tampere, Finland, October 2013.
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.pdf ]
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[5]
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Shaoteng Liu, Axel Jantsch, and Zhonghai Lu.
Analysis and evaluation of circuit switched NoC and packet switch
NoC.
In Proceedings of Euromicro Digital System Design Conference,
Santander, Spain, September 2013.
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.pdf ]
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[6]
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Martin Radetzki, Chaochao Feng, Xueqian Zhao, and Axel Jantsch.
Methods for fault tolerance in networks-on-chip.
ACM Computing Surveys, 46(1):8:1--8:38, July 2013.
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DOI |
http ]
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[7]
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Chaochao Feng, Zhonghai Lu, Axel Jantsch, Minxuan Zhang, and Zuocheng Xing.
Addressing transient and permanent faults in NoC with efficient
fault-tolerant deflection router.
IEEE Transactions on Very Large Scale Integration Systems
(TVLSI), 21(6):1053--1066, June 2013.
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.pdf ]
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[8]
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Abbas Eslami Kiasari, Axel Jantsch, and Zhonghai Lu.
Mathematical formalisms for performance evaluation of
networks-on-chip.
ACM Computing Surveys, 45(3), June 2013.
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DOI |
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[9]
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Abdul Naeem, Axel Jantsch, and Zhonghai Lu.
Scalability analysis of memory consistency models in NoC based
distributed shared memory SoCs.
IEEE Transactions on Computer Aided Design of Integrated
Circuits and Systems, 32(5), May 2013.
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.pdf ]
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[10]
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Abbas Eslami Kiasari, Zhonghai Lu, and Axel Jantsch.
An analytical latency model for networks-on-chip.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions
on, 21(1):113 --123, January 2013.
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DOI |
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