[1]	D. Pamunuwa, J. Öberg, L. R. Zheng, M. Millberg, A. Jantsch, and H. Tenhunen. Layout, performance and power trade-offs in mesh-based network-on-chip architectures. In IFIP International Conference on Very Large Scale Integration (VLSI-SOC), Darmstadt, Germany, December 2003. [ bib | .pdf ]
[2]	Yutai Ma, Axel Jantsch, and Hannu Tenhunen. A group of subword instructions and design issues for network processing RISC cores. In Proceedings of the IEEE NorChip Conference, November 2003. [ bib ]
[3]	Richard Thid, Mikael Millberg, and Axel Jantsch. Evaluating NoC communication backbones with simulation. In Proceedings of the IEEE NorChip Conference, November 2003. [ bib | .pdf ]
[4]	Tarvo Raudvere, Ingo Sander, Ashish Kumar Singh, and Axel Jantsch. Verification of design decisions in forsyde. In Proceedings of the CODES-ISSS Conference, October 2003. [ bib ]
[5]	Heiko Zimmer and Axel Jantsch. A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip. In Proceedings of the CODES-ISSS Conference, October 2003. [ bib | .pdf ]
[6]	Axel Jantsch. NoCs: A new contract between hardware and software. In Proceedings of the Euromicro Symposium on Digital System Design, September 2003. Invited keynote. [ bib | .pdf ]
[7]	Ingo Sander, Axel Jantsch, and Zhonghai Lu. Development and application of design transformations in ForSyDe. IEE Proceedings on Computers and Digital Technique, 150(5):313--320, September 2003. [ bib ]
[8]	Abhijit K. Deb, Johnny Öberg, and Axel Jantsch. Simulation and analysis of embedded DSP systems using Petri nets. In Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping, June 2003. [ bib ]
[9]	Axel Jantsch. Modeling Embedded Systems and SoCs - Concurrency and Time in Models of Computation. Systems on Silicon. Morgan Kaufmann Publishers, June 2003. [ bib | http ]
[10]	Abhijit K. Deb, Johnny Öberg, and Axel Jantsch. Simulation and analysis of embedded DSP systems using MASIC methodology. In Proceedings of the Design Automation and Test Europe (DATE), March 2003. [ bib ]
[11]	Erland Nilsson, Mikael Millberg, Johnny Öberg, and Axel Jantsch. Load distribution with the proximity congestion awareness in a network on chip. In Proceedings of the Design Automation and Test Europe (DATE), pages 1126--1127, March 2003. [ bib | .pdf ]
[12]	Ingo Sander, Axel Jantsch, and Zhonghai Lu. The development and application of formal design transformations in ForSyDe. In Proceedings of the Design Automation and Test Europe (DATE), March 2003. [ bib | .pdf ]
[13]	Axel Jantsch and Hannu Tenhunen. Will networks on chip close the productivity gap? In Axel Jantsch and Hannu Tenhunen, editors, Networks on Chip, chapter 1, pages 3--18. Kluwer Academic Publishers, February 2003. [ bib | .pdf ]
[14]	Axel Jantsch and Hannu Tenhunen, editors. Networks on Chip. Kluwer Academic Publishers, February 2003. [ bib | http ]
[15]	Juha-Pekka Soininen, Axel Jantsch, Martti Forsell, Antti Pelkonen, Jari Kreku, and Shashi Kumar. Extending platform-based design to network on chip systems. In Proceedings of the International Conference on VLSI Design, January 2003. [ bib | .pdf ]