[1]	Zhonghai Lu and Axel Jantsch. Flit admission in on-chip wormhole-switched networks with virtual channels. In Proceedings of the International Symposium on System-on-Chip 2003, November 2004. [ bib | .pdf ]
[2]	Zhonghai Lu and Axel Jantsch. Flit ejection in on-chip wormhole-switched networks with virtual channels. In Proceedings of the IEEE NorChip Conference, November 2004. [ bib | .pdf ]
[3]	Arseni Vitkovski, Raimo Haukilahti, Axel Jantsch, and Erland Nilsson. Low-power and error coding for network-on-chip traffic. In Proceedings of the IEEE NorChip Conference, November 2004. [ bib | .pdf ]
[4]	Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch, and Hannu Tenhunen. A study on the implementation of 2-D mesh based networks on chip in the nanoregime. Integration - The VLSI Journal, 38(1):3--17, October 2004. [ bib ]
[5]	Abhijit K. Deb, Axel Jantsch, and Johnny Öberg. System design for dsp applications in transaction level modeling paradigm. In Proc. Design Automation Conf. (DAC), pages 466--471, San Diego, California, June 2004. [ bib | .pdf ]
[6]	Ingo Sander, Axel Jantsch, and Hannu Tenhunen. The platform as interface in a SoC design curriculum. In Proceedings of te 5t European Worksop on Microelectronics Education, April 2004. [ bib ]
[7]	Heiko Zimmer and Axel Jantsch. Error-tolerant interconnect schemes. In Jari Nurmi, Hannu Tenhunen, Jouni Isoaho, and Axel Jantsch, editors, Interconnect-Centric Design for Advanced SoCs and NoCs, chapter 6. Kluwer Academic Publisher, April 2004. [ bib | .pdf ]
[8]	Jari Nurmi, Hannu Tenhunen, Jouni Isoaho, and Axel Jantsch, editors. Interconnect-Centri Design for Advanced SoCs and NoCs. Kluwer Academic Publisher, April 2004. [ bib ]
[9]	Abhijit K. Deb, Axel Jantsch, and Johnny Öberg. System design for dsp applications using the MASIC methodology. In Proceedings of the Design Automation and Test Europe (DATE), February 2004. [ bib ]
[10]	Axel Jantsch, Johnny Öberg, and Hannu Tenhunen. Special issue on networks on chip - guest editor's introduction. Journal of Systems Architecture, 50(2-3), February 2004. [ bib | .pdf ]
[11]	Axel Jantsch, Johnny Öberg, and Hannu Tenhunen. Introduction to special issue on networks on chip. Journal of Systems Architecture, 50(2-3), February 2004. [ bib ]
[12]	Mikael Millberg, Erland Nilsson, Rikard Thid, and Axel Jantsch. Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip. In Proceedings of the Design Automation and Test Europe Conference (DATE), February 2004. [ bib | .pdf ]
[13]	Tarvo Raudvere, Ashish Kumar Singh, Ingo Sander, and Axel Jantsch. Polynomial abstraction for verification of sequentially implemented combinational circuits. In Proceedings of the Design Automation and Test Europe Conference (DATE), February 2004. interactive presentation. [ bib ]
[14]	Martti Forsell, Juha-Pekka Soininen, Kari Tiensyriä, Axel Jantsch, Klaus Kronlöf, and Bojidar Hadjiski. Networks on chip: Approaches and challenges. In Research and Development Activities in Telecommunication Systems. VTT Electronics, 2004. [ bib | http ]
[15]	Mikael Millberg, Erland Nilsson, Rikard Thid, Shashi Kumar, and Axel Jantsch. The Nostrum backbone - a communication protocol stack for networks on chip. In Proceedings of the VLSI Design Conference, Mumbai, India, January 2004. [ bib | .pdf ]
[16]	Ingo Sander and Axel Jantsch. System modeling and transformational design refinement in ForSyDe. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23(1):17--32, January 2004. [ bib | .pdf ]